Electron microscopy
 
Cobalt Silicide Failure Modes in IC devices
- Practical Electron Microscopy and Database -
- An Online Book -
Microanalysis | EM Book                                                                                   https://www.globalsino.com/EM/        


=================================================================================

 

Depending on specific processing conditions, various failures related to cobalt silicides can exist in IC devices, resulting in significant leakage (or short) or open:
         i) Failure of cobalt silicidation.
         ii) Void-formation-induced failure in cobalt silicidation.
         iii) Failure due to cobalt silicide stringers and spikes.
         iv) Titanium silicides, in general, induce higher compressive strain than cobalt silicides [1]. The induced strain can be a source for dislocation nucleation in silicon if the silicidations are carried out at high temperatures [2].
         v) Cobalt segregates at wafer surface, but such surface segregation is negligible after a fast ramp-down (RTA). [3]
         vi) Cobalt is left in bulk after a treatment with a slow furnace ramp-down. [3]
         vii) Cobalt segregates and precipitates at oxide-silicon interface after thermal treatment. [3]
         viii) Cobalt segregates and precipitates at defects (e.g. dislocations) in bulk. [3]
         ix) Co diffused through 4, 10, 100 nm SiO2 into Si bulk. However, the Co contamination did not affect oxide tunneling voltages. [4]
         x) High concentration of Co on Si substrate, before oxide growth, degraded both oxide and substrate properties [5,6], resulting in excess leakage.

 

 

 

 

 

 

 

 

[1] A. Steegen, I. De Wolf, and K. Maex, “Characterization of the local mechanical stress induced during the Ti and Co/Ti salicidation in sub-0.25 μm technologies,” J. Appl. Phys., vol. 86, pp. 4290–4297, 1999.
[2] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide induced pattern density and orientation dependent transconductance in MOS transistors,” IEEE IEDM Tech. Dig., pp. 497–500, 1997.
[3] Bernd O. Kolbesen, Crystalline defects and contamination: Their impact and control in device manufacturing: proceedings of the Satellite Symposium to ESSDERC 93, Grenoble, France Paperback, 1993.
[4] Cor L. Claeys, High Purity Silicon VI: Proceedings of the Sixth International Symposium, Volumes 2000-2017.
[5] M. M. Heyns, T. Bearda, I. Cornelissen, S. De Gendt, D. M. Knotter, L. M. Loewenstein, M. Lux, P. W. Mertens, S. Mertens, M. Meuris, M. Schaekers, P. Snee, I. Teerlinck and R. Vos, International Electron Devices Meetings, p. 325, 1998.
[6] M. Horuai, et. al., Jpn. J. Appl. Phys., 27, L2361 (1998).

 

=================================================================================