Practical Electron Microscopy and Database

Cobalt silicidation can induce void formation at the edge of oxide pattern [1] and at the edge of the sidewall spacer of MOSFET devices [2]. The void formation during post-annealing is favorable in reducing both the number of excess silicon vacancies and the tensile stress generated in the silicon substrate during silicidation. Cobalt silicidation generates Si vacancies in the adjacent Si region that is in contact with cobalt disilicide layer. [3] On the other hand, boundaries, e.g. free surfaces at STI (shallow trench isolation) and sidewall spacer edge, could lower the nucleation barrier for voiding. The void can cause serious junction leakage [1] or serve as a resistance in the current–voltage characteristics of devices [2].

Byun et al. [1] reported that the second RTA (rapid thermal annealing), which was used to convert cobalt monosilicide (CoSi) to cobalt disilicide (CoSi₂), induced rapid silicon migration from silicon to cobalt monosilicide, resulting in a void. Figure 2796a presents a cross-sectional TEM image taken along [110] direction showing voids generated at the edge of the sidewall spacer of a MOSFET structure during post-annealing at 850 °C for 60 min.

Pramanick et al. [4] observed that the voids existed at the Co/Si → CoSi₂, CoSi₂ → CoSi, and CoSi → CoSi₂ phase boundaries.

The void shown in Figure 2796b presents a failure issue within the cobalt silicide layer of the cobalt silicide/polysilicon/silicon/insulator stack. This defect is critical in the silicide formation for CMOS devices. The image clearly illustrates spiking and voiding within the cobalt silicide, which can occur due to the high-temperature processing steps used during silicide formation. These defects are problematic because they can disrupt the electrical performance of the device by causing increased resistance or complete electrical disconnection at contact points. The voiding is likely a result of non-uniform diffusion during the silicidation process, where the cobalt interacts with the silicon substrate. In advanced semiconductor processes, controlling the formation of voids is essential to ensure the reliability of silicide contacts, as voids can lead to open circuits or degraded device performance. This voiding and spiking issue is one of the reasons for the transition from cobalt silicide to alternatives like nickel silicide, which is more stable at reduced feature sizes (e.g., 65 nm technology nodes and beyond). Nickel silicide offers advantages like lower resistance, better uniformity, and reduced sensitivity to line width variations, which helps mitigate the voiding and spiking phenomena observed with cobalt silicid.

[1] J. S. Byun, J. M. S., K. Y. Youn, H. H., J. W. Park, and J. J. Kim, J. Electrochem. Soc. 143, L56 (1996).
[2] Yeong-Cheol Kim, Jongchae Kim, Jun-Ho Choy, Ju-Chul Park, and Hong-Min Choi, Effects of cobalt silicidation and postannealing on void defects at the sidewall spacer edge of metal–oxide–silicon field-effect transistors, Applied Physics Letters, 75(9), 1270, (1999).
[3] J. W. Honeycutt and G. A. Rozgonyi, Appl. Phys. Lett. 58, 1302 (1991).
[4] S. Pramanick, Yu. N. Erokhin, B. K. Patnaik, and G. A. Rozgonyi, Morphological instability and Si diffusion in nanoscale cobalt silicide films
formed on heavily phosphorus doped polycrystalline silicon, Appl. Phys. Lett. 63 (14), (1993) 1933.
[5] Raghaw S. Rai and Swaminathan Subramanian, Role of transmission electron microscopy in the semiconductor industry for process development and failure analysis, Progress in Crystal Growth and Characterization of Materials, 55, pp.63-97, 2009.