For failure analysis of memories, the absolute address of a failed bit in arrays can essentially be obtained by electrical failure analysis (EFA) techniques with electrical testing. However, this address needs to be converted to a physical address (x and y coordinates) on the chip for physical failure analysis (PFA) and root cause identification. Figure 3294 shows schematic illustration of failure analysis of memories.

Figure 3294. Schematic illustration of failure analysis of memories.

In memories, some failures such as single, double and small-cluster bit failures are very common and are invisible under optical microscopes. Node-to-node and node-to-power line shorting can occur through CMP scratches [1]. This type of shorting is normally on the order of a tenth of a micron or larger. Electrical opens can be caused by dangling contacts of bitlines and PMOS [2,3].

[1] Soon-Moon Jung, Jun-Sup Uom, Won-Suek Cho, Yong-Joon Bae, Yeon-Kyu Chung, Kwang-Suk Yu, Kil-Yeon Kim, Kyung-Tae Kim, A study of formation and failure mechanism of CMP scratch induced defects on ILD in a W-damascene interconnect SRAM cell, in: Proceedings of the 39th Annual International Reliability Physics Symposium, Orlando, FL, 2001, p. 42.
[2] Z.G. Song, G. Qian, J.Y. Dai, Z.R. Guo, S.K. Loh, C.S. Teh, S. Redkar, Application of contact-level ion-beam induced passive voltage contrast in failure analysis of static random access memory, in: Proceedings of the Eighth International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Singapore, 2001, p. 103.
[3] C.S. Teh, Z.G. Song, J.Y. Dai, Z.R. Guo, S. Redkar, Polyresidue-induced contact failure in 0.18 lm technology, in: Proceedings of the Eighth International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Singapore, 2001, p. 117.