Google's Edge TPU hardware

Google's Edge TPU Hardware
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Google's Edge TPU hardware is composed of three main components of the neural node, the multiplier, the adder and the activation function. [1] Figure 3822a shows Google's Edge TPU hardware.

Pipeline in Google's Edge TPU hardware

(a)

Pipeline in Google's Edge TPU hardware

(b)

Figure 3822a. Google's Edge TPU hardware: (a) The chip [1], and (b) Edge TPU SoM Block Diagram [2].

Figures 3822b and 3822c shows the adder and pipeline in Google's Edge TPU hardware.

Adder in Google's Edge TPU hardware

Figure 3822b. Adder in Google's Edge TPU hardware.

Pipeline in Google's Edge TPU hardware

Figure 3822c. Pipeline in Google's Edge TPU hardware.

AutoML has been used to customize EfficientNets for Edge TPU to obtain better latency and accuracy (shown in Figure 3822).

Pipeline in Google's Edge TPU hardware

Figure 3822. EfficientNet-EdgeTPU-S/M/L models achieve better latency and accuracy than existing EfficientNets (B1), ResNet, and Inception by specializing the network architecture for Edge TPU hardware. In particular, the EfficientNet-EdgeTPU-S achieves higher accuracy, runs 10x faster than ResNet-50. [3]

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[1] Google Coral Edge TPU explained in depth, https://qengineering.eu/google-corals-tpu-explained.html.
[2] https://www.cnx-software.com/2019/03/04/buy-google-edge-tpu-coral-development-board-usb-accelerator/.
[3] https://blog.research.google/2019/08/efficientnet-edgetpu-creating.html.

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