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Mirza [1] generated statistical collections for each wafer lot with stack maps, where each location is given by the number of wafer maps in the lot that have a good chip at that location. The number of wafers with good dies on a particular location should be randomly distributed over the stack map if there were no systematic dependencies. Figure 4218a shows a stack map for a randomly chosen lot with a total of 18 wafers. The stack map had some locations on edges at which no wafer had a good die, indicating misprocessing at these edge locations for all wafers in the lot. The consistency of die failures on edges was due to edge effects:
         i) Wafers are often carried between processing steps in plastic carriers. The wafers are held between grooves in carriers such that only wafer edges touch the grooves. Particles can enter the carriers from sides only and are electrostatically attracted to the nearest edge of the wafer. Thus particles, clustered at the wafer edges, are likely to result in the formation of defects at the edges with a higher density than on any other location on the wafer.
         ii) Photolithography defect arises due to diffraction caused by mask edges of the ultraviolet light used for exposure.

Figure 4218a. A stack bin map for a lot of 18 wafers. [1]

Binary stack maps can be formed in different ways:
         i) If there is no yield dependency by location in a given lot, then each location on its stack map can be given by a binomial random variable Q defined by, [1]
          ----------------------------------------- [4218a]
where,
         P -- The average yield for the lot.
         N -- The number of wafers in the lot.
Any location on the stack map, which has yield greater than E(Q) in the stack map, is represented by a "1", and a location, which has yield less than E(Q), is represented by a "0". The binary representation of the stack map should have a random distribution of 1's and 0's if no yield variation by location exists.
         ii) Gradient contrast stack map by a threshold. The gradient contrast appears because the zero yield regions may occur at different locations and have different shapes and sizes on different wafers. The existence of regions of low and high yields on the stack maps can be explained by map overlap among the locations of zero yield regions on individual wafers of a given lot.

The most informative spatial dependency on individual wafers exists in the form of failure regions.

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[1] Agha Irtaza Mirza, Spatial Yield Modeling for Semiconductor Wafers, thesis, 1995.