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With the increase in the complexity of the semiconductor device processes and the increase in the challenge to satisfy high market demands, enhancement in yield has become a critical factor. [1] Estimation of yield and faster yield ramp are critical. With new technologies introduced and fabricated, the yields observed could be as low as 20% of the production [1]. Therefore, with 80% of the product being lost, advanced and faster schemes should be developed for detection and correction of these faults, since fault isolation and failure analysis of defective wafers may cause unbearable time loss in IC-product development. To achieve increased yields, various methods are adopted like modifying layout shapes, design rules, conditions of processes [2,3] etc. Beyond the improvement of the manufacturing-related processes, the techniques for PFA also needs to be revised according to the new needs. Therefore, it is necessary to develop effective and efficient techniques to identify root cause and significantly shorten the time of fault diagnosis process, and thus support yield improvements and shorten yield-ramping time in time-efficiency. Various fault localization techniques for faster problem identification have been investigated.

Once yield analysis has been completed, PFA is used to identify the root cause of failures. The PFA engineers use various effective fault identification and localization techniques to localize the faulty block with high accuracy. For those who care about defect location only, logic diagnosis should be sufficient as long as the suspect net or area is small enough for the physical failure analysis (PFA) workflow to manage. [5] However, for those who concern defect classification and better physical resolution so the PF A engineer can reduce the suspect net or area, speed up cycle time, and improve the PFA success rate [6], layout-aware diagnosis can be a better choice because it offers improvement in resolution from just a logical net to a specific layout segment and more specific defect classification.

However, failure identification is a tedious and time-consuming process. An efficient, accurate and fast analysis tool becomes more essential to reduce IC design and/or process faults, and thus improves IC yield. Some new tools, such as Synopsys’s Avalon, have been developed to improve design debug accuracy and reduces root cause analysis time for yield limiters [4]. Figure 4222a shows the two fault diagnosis processes:
         i) Identifying the fault sites without physical failure analysis.
             i.a) Layout-aware diagnosis can narrow the suspects down to specific layout segments for accuracy improvement.
         ii) Identifying the fault sites efficiently by assessing the cause from the diagnosis results.

Figure 4222a. Two fault diagnosis processes.

Conventional yield analysis techniques face limitations, especially during early stages of a technology when multiple yield limiting factors are mixed together. Some challenges exist in the current failure analysis flow and potential solutions can be given:
         i) High level of diagnosis noise, which could impact analysis result. It's very common for scan diagnosis to contain multiple symptoms and suspects. To remove the noise from the diagnosis, Root Cause De-convolution (RCD) is needed (Figure 4222b). Similar to a noise filter, RCD eliminates this noise and identifies the underlying root cause distribution. The RCD algorithm with RCD pareto can:
            i.a) Ranks all suspected root causes so that we can prioritize all root causes. We need to increase the PFA hit rate by ignoring irrelevant locations with non-target root causes.
            i.b) Generates a defect distribution by calculating the probability of observing diagnosis results based on design-and test-weighted statistics. [7] Given a specific root cause, the probability of a specific suspect can be calculated by critical area per net segment per layer. For
instance, the probability of observing a specific suspect will be equal to the suspect's critical area for the specific root cause per layer, divided by the total critical area for all possible suspects. The probability of seeing all the suspects in the reports and can be calculated to determine an overall probability number. By leveraging the suspect with the highest ranking to the likely root cause, the noise-like suspects can be easily eliminated.
            i.c) Automatically determines the underlying root causes in represented devices from a population of failing test data alone.
            i.d) Find the dies that are most likely to represent a root cause of interest and sort the suspects in order of probability for a particular root cause.
            i.e) Provides more flexibility to handle the dies with multiple symptoms and suspects.
            i.f) Allows to select PFA candidate based on probability of specific root cause.
         ii) Taking the right actions before a time-consuming and unpredictable PFA procedure.
         iii) Not all defective parts are qualified for PFA. A PFA candidate must have a single diagnosis suspect, a high diagnosis score, and a small suspect area in the layout.
         iv) Not all qualified candidates result in successful PFA since not all root cause can be found in PFA.
         v) There is no guarantee that all successful PF A results will point to a single root cause.
         vi) Not all converged root causes are related to systematic defects. Random defect analysis is redundant and doesn't help at all. Therefore, we need to choose the relevant PFA candidate to avoid unnecessary iterations for random defects.
         vii) Most PFA processes are destructive. If the defect can't be found on the first try, the sample could be ruined and the overall cycle time could be increased.
         viii) The dies, which contains multiple symptoms and suspects, should unlikely to be chosen as PFA candidate. This can also be true if the local electrical connection give multiple root causes.

Figure 4222b. Root Cause De-convolution (RCD).

Therefore, a methodology to overcome these uncertainties and reduce excursion yield loss in a predictable time is needed. Physical-aware scan diagnosis [8-9] becomes critical because it is able to localize single defects within a logic circuit. However, due to the inherent ambiguity of scan diagnosis results, multiple suspects are often called out for a real defect, which complicates the analysis. In recent years, intelligent volume diagnosis algorithms have been developed to data-mine the diagnosis results.

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 [1] Ankush Oberai and Jiann-Shiun Yuan, Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield, Electronics, 7, 28, doi:10.3390/electronics7030028, 2018.
[2] Rencher, M. Physical DFY Technique Improve Yields. EE Times, March 2004.
[3] Asami, T.; Nasu, H.; Takase, H. Oyamatsu. In Proceedings of the IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, Boston, MA, USA, 4–6 May 2004; pp. 448–452.
[4] Auvray, E.; Armagnat, P.; Cason, M.; Villab, E.; Jothi, M.; Brugel, M. Evolution of navigation and simulation tools in failure analysis. In Proceedings of the 27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Handel-Halle, Halle (Saale), 19–22 September 2016; pp. 1–8.
[5] Ting-Pu Tai, Case study of reducing excursion yield loss, 2015 China Semiconductor Technology International Conference, DOI: 10.1109/CSTIC.2015.7153450, 2015.
[6] Experiences with Layout-Aware Diagnosis - A Case Study, Yi-Jung Chang and Man-Ting Pang, UMC, Mike Brennan and Albert Man, * AMD, Inc., Martin Keim, Geir Eide, Brady Benware, and Ting-Pu Tai, Mentor Graphics, EDFA, Volume 12, No. 2.
[7] White paper: Root Cause Deconvolution - The Next Step In Diagnosis Resolution Improvement, Geir Eide, Mentor Graphics.
[8] G Eide, “Avoid throwing darts at a black hole by using Diagnosis- Driven Yield Analysis”, Solid State Technology, July 2010.
[9] J Mekkoth, M Krishna, J Qian, W Hsu, CH Chen, YS Chen, N Tamarapalli, WT Cheng, J Tofte, M Keim, “Yield learning with layout-aware advanced scan diagnosis,” Proc Int Symp for Testing and Failure Analysis, pg 412-418, 2006.