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In the semiconductor industry, visible surface defects are mainly being inspected manually, which may result in inevitably erroneous classification. Many machine learning techniques-based recently pioneered arts in academia have been proposed to aid wafer failure pattern classification.

Automatic methods, capable of quickly assessing the root causes of the defects by analyzing the data obtained from automated defect scanning, are very important to semiconductor manufacturing because these automatic methods can lead to a considerable reduction in operator workload and improvements in accuracy and consistency. On the other hand, these methods help engineers quickly assimilate manufacturing data from defect inspection tools and then translate those data into manufacturing solutions, enhancing both yield and reliability [1-3]. Note that, although many studies on automatic classification have been conducted, it is still hard to classify when two or more patterns are mixed on the same map.

There have been numerous studies on the automatic retrieval of spatial features of defect clusters in semiconductor manufacturing. Examples of automatic methods are:
         i) Automated defect scanning on wafer maps can quickly examine a wafer using laser light. It can identify the locations of the defects and their relative sizes based on the scattering of the light.
         ii) Automated clustering algorithm via artificial intelligence. [2]
         iii) Empirical clustering algorithm. [4]
         iv) Neural networks for spatial defect pattern recognition. [5]

In the method of automated defect scanning in wafer map, some problems are still remaining:
         i) Deep learning-based techniques separate the generation process from the classifier calibration, and even worse, synthesis may lead to the label perturbation. For this issue, recently investigated few-shot learning technique (see page4244) which is related to imbalanced learning [6] can alleviate.
         ii) Many unlabeled wafer maps are idle.

To address the challenges, Geng et al. [7] combine the few-shot learning and self-supervised learning algorithms (see page4235), and design an end-to-end wafer failure pattern classifier as shown in Figure 4260. The advantages of their method are:
         i) An end-to-end wafer map defect pattern classification flow is applied.
         ii) The self-supervised learning technique is embedded into the classification flow to make full use of the tremendous unlabeled wafer maps in order to reduce the human labor efforts.
         iii) The few-shot learning paradigm is incorporated to overcome the data imbalanced issue.

Figure 4260. Wafer failure pattern classifier. [7]

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[1]  P. B. Chou, A. R. Rao, M. C. Sturenbecker, F. Y. Wu, and V. H. Brecher, “Automatic defect classification for semiconductor manufacturing,” Mach. Vis. Appl., vol. 9, no. 4, pp. 201–214, 1997.
[2] S. S. Gleason, K. W. Tobin, T. P. Karnowski, and F. Lakhani, “Rapid yield learning through optical defect and electrical test analysis,” Proc. SPIE-Int. Soc. Opt. Eng., vol. 3332, pp. 232–242, 1998.
[3] K. W. Tobin, S. S. Gleason, T. P. Karnowski, and D. Guidry, “Using SSA to measure the efficacy of automated defect data gathering,” Micro, vol. 16, pp. 27–33, 1998.
[4] S. Cunningham and S. MacKinnon, “Statistical methods for visual defect metrology,” IEEE Trans. Semiconduct. Manuf., vol. 11, no. 1, pp. 48–53, Feb. 1998.
[5] F. L. Chen and S. F. Liu, “A neural-network approach to recognize defect spatial pattern in semiconductor fabrication,” IEEE Trans. Semiconduct. Manuf., vol. 13, no. 3, pp. 366–373, Aug. 2000.
[6] Y. Wang, Q. Yao, J. T. Kwok, and L. M. Ni, “Generalizing from a few examples: A survey on few-shot learning,” ACM Computing Surveys (CSUR), vol. 53, no. 3, pp. 1–34, 2020.
[7] Hao Geng, Fan Yang, Xuan Zeng, Bei Yu, When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning, DOI: 10.1109/ICCAD51958.2021.9643518, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021.