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Wafer map analysis, on both single pattern and mixed-type pattern maps, is one of the most critical steps for monitoring wafer quality and tracking failures in the semiconductor manufacturing process. Defective dies on wafer bin maps (WBMs) usually cluster into specific spatial patterns, which contain critical information for root cause identification and yield improvement.

Systematic failures are a significant contributor to yield loss in the modern Interstitial Cystitis (IC) wafer fabrication process [16]. As a result, identifying systematic failures (defect clusters) has emerged as one of the top challenges in the modern IC industry [17]. In the IC design process, the process of existing wafer test is the main factor of production cost. The test process could take an additional amount of time and cannot make adjustments of the process immediately. The defect patterns, reflecting failure mechanisms, on wafer bin map are related to yield degradation. Fail bit maps (FBMs) represent the failed cell count during wafer functional probe tests and have been popularly used as one of the diagnosis tools in semiconductor manufacturing for process monitoring, root cause analysis, and yield improvements. The location of the failure point is graphically represented in the feature of the wafer maps. Most companies control the manufacturing processes which occur to any critical defects by identifying the maps so that it is important to classify the patterns accurately. Therefore, wafer map defect recognition is an import part of semiconductor production. Lots of information in wafer maps can quickly help engineers to identify what failure type it is. In this case, the engineers inspect the maps directly. However, it is difficult to check many wafers one by one because of the increasing demand for semiconductors.

In some cases, WBMs (wafer bin map) exhibit the signature patterns of specific processes causing defects [29-30]. Therefore, comparing the process histories of similar failures in a database may provide sufficient information to perform defect diagnosis and root cause analysis without predetermined classes [31]. Defect clusters are consistent and repeated failure patterns on wafers caused by systematic faults in the manufacturing process [18]. Such faults are process-related phenomena of different types, which may, for instance, be attributed to process excursions, handling errors, faulty equipment and/or insufficient quality materials [19][20]. Neighbour clustering and image processing are the common techniques used to obtain features on each specific defect cluster. [21-23] The wafer map failure patterns can be classified by:
         i) Center pattern. It is a block of defect near the central area of a wafer.
         ii) Donut pattern. It is a hollow and block defects located within the wafer.
         iii) Edge-loc pattern. It is systematic defects with cluster at the wafer edge.
         iv) Edge-ring pattern. It is systematic defects with moon shape at the wafer edge.
         v) Loc pattern. It is a cluster defect within the wafer.
         vi) Near-full pattern. The defects cover most of the wafer.
         vii) Random pattern. A small number of defective areas are located on a wafer randomly.
         viii) Scratch pattern. It is a defect in a straight line or curve.
         ix) None pattern. In the no systematic pattern, the pattern was caused by random particles falling on a wafer, and defects are randomly distributed.

Classification of semiconductor defect clusters can be achieved by applying techniques such as neural networks, rule induction, decision trees, Hough Transform and so on. [24-27] Figure 4271a shows the frequency of publications, from year 2001 to 2020, clearly indicating the rise in research interest in this domain [13]. This graph is extracted from SCOPUS database for keyword “wafer defect classification” and filtered by selecting the articles published in engineering and computer science domain resulting in total 167 articles [14].

Wafer map failure pattern recognition (WMFPR) is also called as wafer failure pattern detection (WFPD). The WMFPR plays a key role in preventing yield loss excursion events for semiconductor manufacturing. The approach has mainly been classified into two branches:
          i) Model-based pattern recognition. In this method, a pre-defined probability distribution function is used for each wafer pattern and the best statistical model is determined by comparing the models by using information criterion.
          ii) Feature extraction-based pattern recognition. In this method, a large amount of pioneered suggestions [1-7] have been presented. However, the feature design or extraction has a significant impact on the accuracy of failure pattern classification. These feature extraction-based works can be further divided into three categories:
             ii.a) Manually-crafted feature-driven. The domain knowledge of expert engineers is needed when manually designing the feature.
             ii.b) Automatic feature extraction-based, e.g. deep learning methods, especially deep convolutional neural networks (CNNs). For instance, Wu et al. [1] develop radon-based and geometry-based features, while Yu et al. [2] define geometrical, gray, texture, and projection features, and merge the features by their proposed dimension reduction and feature extraction methods. [4-7]
             ii.c) Combination between manual and automatic methods. For instance, some of the manually-crafted feature-based methods, assigned to experienced engineers, work in an unsupervised fashion. [3]
             ii.d) Nonparametric Bayesian clustering based on the Dirichlet process Gaussian mixture model, and hierarchical clustering based on the symmetric Kullback–Leibler divergence. [28]

Figure 4271b. General similarity wafer search and wafer map failure pattern recognition.

Figure 4271c shows a proposed approach used in WMFPR study. In the data processing, with WM-811K dataset, which Jo and Lee had [10], each pixel on the colored images has only three types of value. If the pixel has 0 value, the pixel is out of the wafer. If the pixel has one value, the pixel represents a normal die. If the pixel has 2 values, the pixel represents defect die. These values that pixels have are categorical variables. Therefore, they changed the number of channels in images to 3, each channel represents out of the wafer, normal die, and defect die, like one-hot encoding. To match the size of the images since the images in the dataset have various sizes. they changed the image size to 64 by 64.

Figure 4271c. Proposed approach used in WMFPR study. [9]

It is important to note that defect categories have different frequencies of occurrence and many classes lack sufficient associated wafter maps, resulting in a biased classifier where the decision boundary can be extremely altered by the majority classes. Therefore, an inaccurate defect classification result would be reported by the poorly calibrated model.

Figure 4271d shows the flowchart of WMFPR which is based on a two-stage framework. Stage 1 determines whether a wafer map exhibits a failure pattern, while Stage 2 identifies the pattern type. In this flowchart, an SVM (support-vector machines) is used as a classifier. During the training phase, the SVMs determine the support vectors in the training data, which are applied to predict new wafer maps during the test phase. The main advantage of the two-stage framework is that the parameters can be trimed to optimize the tradeoff between the false-positive rate and the false-negative rate at Stage 1.

In the WMFPR, false-positive (FP) is defined as the rate of misclassifying Nonpattern as Pattern, whereas false-negative (FN) is the rate of misclassifying Pattern as Nonpattern. The detection error tradeoff (DET) curve can be obtained. Figure 4271e (a) shows the combined confusion matrix for the test set (overall accuracy = 94.63%). In the figure, the annotations (ground truth) are shown in the left column, and the predictions by the proposed system are in the top row. The diagonal elements represent the recognition rate of each type. It shows that Local was frequently confused with other failure types. Figure4271e (b) shows several wafer maps that were misclassified as Local. The wafer maps were misclassified, but users generally accept the prediction because these wafer maps seem to saddle across the boundary of two types. This indicates that the users' satisfaction would likely be higher, as indicated by the overall accuracy (94.63%).

(a)

(b)

Table 4271. Patterns commonly reflecting specific process failure information.

Figures 4271f and 4271g show a typical wafer pattern maps from WM811K dataset and STMicroelectronics dataset.

Figure 4271f. Sample wafer examples for different pattern types. [12]

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