Figure 4916a shows that a transistor failure could not be identified by either LIT nor PEM technique alone since both techniques show hotspots of the multiple transistors of the circuit. However, both technique shows a common hotspot from the same PMOS transistor (Location 2 in Figure 4916a (a) and location 6 in Figure 4916a (b)). The physical fail of this transistor has been verified by passive voltage contrast, in Figure 4916b (a), showing a bright contact contrast of the PMOS transistor gate. Such good gates (not shown here) should present a dark contrast instead of a bright contrast. The cross-section SEM image in Figure 4916b (b) indicated a leakage path to substrate, which caused the abnormal contrast in Figure 4916b (a).

Figure 4916a. (a) LIT image and (b) PEM image. [1]

Figure 4916b. (a) PVC image and (b) SEM image in a dual beam system. [1]

The simplified schematic diagram of the IC device in Figure 4916c shows the relationship between the hotspots and emissions sites in Figure 4916a. The hotspots 1 and 3 were directly connected to the gate of the failing PMOS transistor, while the emissions 4 and 5 were the secondary effect of the gate signal of the failed PMOS transistor.

Figure 4916c. Simplified schematic diagram of the IC device. [1]

[1] Paul Hubert P. Llamera and Camille Joyce G. Garcia-Awitan, Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission, ISTFA™ 2019: Conference Proceedings from the 45th, (2019).