Short fail in DRAM

Short Fail in DRAM
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Short failure in DRAM is often caused by misalignment of isolation layer or mask contamination. [1] Bridge that are caused by extra metal deposition or isolation breakdown. Bridge defects can occur between BL (Bit Line) contact and BCAT (Buried Cell Array Transistor), caused by isolation breaking. [2]

Figure 2015a (b) shows that cross bridge defects between BL and WL are induced by the lack of metal etch back (MEB) or poly etch back (PEB) of BCAT caused by various particle. [1] Due to the particle, silicon-nitride (SiN) is not filled on the BCAT material, which caused a short fail. Such defects are mainly observed in the first test step and initially appears as column failure. In this situation, if WL located in failure marking is turned on, V_BL goes high level due to charge sharing and sensing operation because high level of WL and BL are electrically connected. On the other hand, if adjacent WL in failure marking is turned off, _BL goes low level because of low level of WL.

Figure 2015a (c) shows extended cross-defects that there are complex mutual reactions between defects such as both WL and BL failure. It can cause errors at the system level with a very high probability even though there is ECC. The extended cross-defects accompanied by two WL defects have been frequently found as shown in Figure 2015b, where the particle exists in the BL contact area.

Figure 2015a. Schematic of 1 Transitor-1 capacitor DRAM (a) with C_S and C_BL (b) with general cross-defect [4], (c) extended cross-defect with 2-WL failure due to metal penetration. [1]

Figure 2015b. Extended cross-defect with 2-row failure by metal penetration. [1]

Figure 2015c shows timing diagram for data-1 read operation related to V_BL. Figure 2015c (a) illustrates a level of normal BL for data-1. Figure 2015c (b) shows the case of data-1 read operation with defective adjacent WL turned on. Figure 2015c (c) shows the case of defective WL turned on. The fact that defective adjacent WL is turned on means that failure WL level is low. Therefore, the V_BL drops significantly from charge sharing to sensing due to connection with low WL level even if cell charge is high. On the other hand, if defective WL turns on, failure WL level is high. Thus, V_BL level goes up with help from charge sharing to sensing due to connection with high level of WL.

Figure 2015c. Timing diagram illustrating the BL level for data-1 read operation. (a) without cross-bridging defect, (b) adjacent defective WL turned on, and (c) defective WL turned on.[1]

[1] Jaehoon Lee, Jinseon Kim, Dongguk Han, Seunghun Lee, Sunwoo Kim, Jingyeong Seol, Seungjin Lee, Kyoungrak Cho, Incheol Nam, Daesun Kim, Beomseop Lee, Heeil Hong, and Sangjun Hwang, A Failure Caused by Extended Cross-Defect in DRAM, ISTFA 2023: Proceedings of the 49th International Symposium for Testing and Failure Analysis Conference November 12—16, 2023, Phoenix, Arizona, USA https://doi.org/10.31339/asm.cp.istfa2023p0187.
[2] Zaid Al-Ars, “DRAM-specific Space of Memory Tests”, in ITC, (2006)

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