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Figure 2220a shows an architecture of a DRAM bank with a (72, 64) In-DRAM ECC (IECC) module. When the memory controller issues a write command of a 64-bit data, the IECC module writes a 72-bit data by adding a generated 8-bit parity to the memory array. This data plus the parity bit is called codeword. In case of a read operation, the IECC module reads a 72-bit data, and checks and corrects the error before sending a 64-bit data to the memory controller. [1] There are two types of Hamming codes that are commonly used as IECC:
          i) A 128-bit data with an 8-bit parity code (6.25% overhead) to deal with single error correction (SEC).
          ii) A 64-bit data with an 8-bit parity code (12.5% overhead) to enable SEC with double error detection (SECDED). These two codes are popular because they can be implemented with low area and latency overheads in DRAM. [2]

Figure 2220a. DRAM bank with IECC module. [3]

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[1] Jeong, Sangmok, SeungYup Kang, and Joon-Sung Yang. "PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code." 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020.
[2] Cha, Sanguhn, et al. "Defect analysis and cost-effective resilience architecture for future DRAM devices." 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2017. I. S. Jacobs and C. P. Bean, “Fine particles, thin films and exchange anisotropy,” in Magnetism, vol. III, G. T. Rado and H. Suhl, Eds. New York: Academic, 1963, pp. 271–350.
[3] Hanbyeol Kwon, Kwangrae Kim, Dongsuk Jeon and Ki-Seok Chung, Reducing Refresh Overhead with In-DRAM Error Correction Codes, 2021 18th International SoC Design Conference (ISOCC), DOI: 10.1109/ISOCC53507.2021.9613990, (2021).