Two-Layer Resist Etch-Back Planarization - Integrated Circuits and Materials - - An Online Book - |
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| Integrated Circuits and Materials http://www.globalsino.com/ICsAndMaterials/ | ||||||||
| Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix | ||||||||
================================================================================= As shown in Figure 2317, the steps in the technique of two-layer resist etch-back planarization are:
Figure 2317. Two-layer resist etch-back planarization. [1]
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[1] André Schiltz, Laëtitia Palatini, Maryse Paoli, Maurice Rivoire, and Alain Prola, Plasma etch-back planarization coupled to chemical mechanical polishing for sub 0.18 μm shallow trench isolation technology, Journal of Vacuum Science & Technology A 18, 1313, doi: 10.1116/1.582346, (2000).
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