CDSEM (Critical-Dimension-SEM)
- Integrated Circuits and Materials -
- An Online Book -
| Integrated Circuits and Materials http://www.globalsino.com/ICsAndMaterials/ |
Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix
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CD-SEM is a tool used for Over the past many years, some have stated that CD-SEM is almost at the end of its usefulness. A couple of past works showed that the spatial resolution of CD-SEMs has stagnated in recent years, and is falling behind the requirements
of Moore’s law. [17, 18] CDSEM measurements are limitated and thus causes repeatability
to decline in some cases: [2] There are three components in total repeatability (3-σtotal): Due to a continuous reduction in feature size, a reduction in
resist film thickness (FT) is required to prevent large aspect ratios that lead to pattern collapse, especailly <30 nm resist FT is expected when advancing to high NA EUVL. This brings along associated challenges with: [9] |
Table 2360. CD-SEMs.
| Functions | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Measurement purpose | Features per die | Features per dose condition | Voltage (eV) |
Resolution | Solution to CD-SEM metrology | Throughput | Pixel # x |
Pixel # y |
Pixel size x (nm) |
Pixel size y (nm) |
Magnification | Image size | Total area per image | Measurement repeatability | MAM timec | Visual field positioning accuracy | Beam energy range | Probe current | 3-σshort | Noise | Visual field misalignment |
Autofocus variation | Brightness correction variation |
Functions | Factors causing inaccuracy | Others | Best-known settings | Tool model | Company | Reference |
| General | ≤1keV | |||||||||||||||||||||||||||||
| LERg | 27 | 164 | CG5000 | Hitachi | [20] | |||||||||||||||||||||||||
| Postdevelop L/S CD |
500 | 512 | 512 | 0.88 | 0.88 | 300 | CG5000 | Hitachi | [20] | |||||||||||||||||||||
| Postdevelop L/S LER |
500 | 512 | 512 | 0.80 | 5.0 | 300 × 57.2 | CG5000 | Hitachi | [20] | |||||||||||||||||||||
| Postdevelop LCDU |
294 | 1470 | 500 | 512 | 512 | 0.66 | 0.66 | 400 | CG5000 | Hitachi | [20] | |||||||||||||||||||
| Postetch LCDU |
294 | 1470 | 800 | 512 | 512 | 0.66 | 0.66 | 400 | CG5000 | Hitachi | [20] | |||||||||||||||||||
| Sub-10 nm | Modeling SEM waveforms for very small features | [15] | ||||||||||||||||||||||||||||
| Aberration correction | [19] | |||||||||||||||||||||||||||||
| EUV nodes | 0.8 | 0.8 | 83K | 1638 nm × 1638 nm at 2048 × 2048 pixels | 128 μm2 | 500-V | 8.0-pA | uLWRf & CD | Depending on resist film thickness and the underlayer | Fractilia MetroLER software 2.3.0 & averaging 50 images | IMEC | CG-6300 CDSEM | Hitachi | [9] | ||||||||||||||||
| < 28 nm | Improved by magnification calibration | Auto-Stigma function on CD SEM is used to compensate for ~80-90% astigmatism | Fine pattern measurements on the wafer are automated | Linewidth precision | Charging on DDe | [3 - 8] | ||||||||||||||||||||||||
| For 65-nm node | 2.0 nm | 55 wafers per hour | Static 1.0 nm (3 σ) | < 5 s | ±1 μm | 300 V to 1,600 V | 0.55 nm | 0.3 nm | 0.4 nm | 0.25 nm | 0 nm | Edge CD and roughness of pattern: gates LERa, gates LWRb | Safety standard, FOUPd type mini environment system, software | Hitachi | [2] | |||||||||||||||
| CG6300 | Hitachi® | [1] | ||||||||||||||||||||||||||||
| a. LER: Line-edge roughness of line patterns. b. LWR: Line-width roughness of line patterns. c. MAM: move, acquire, measure. d. FOUP: Front opening unified pod. e. DD: Dual damascene. Distortion of SEM images is formed on the non-uniformly distributed charged wafer. f. uLWR: unbiased line width roughness. g. LER (line edge roughness). |
Table 4834b. xx.
It is expected that, for high NA EUVL, the challenges can be subdivided into: [9]
Figure 2360b shows user interfaces of CDSEM systems.
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| [1] Murat Pak, Wesley Zanders, Patrick Wong, Sandip Halder, Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars, Micro and Nano Engineering, https://doi.org/10.1016/j.mne.2021.100082, 2021. [2] Atsuko Yamaguchi, Ryo Nakagaki and Hiroki Kawada, CD-SEM Technologies for 65-nm Process Node, https://www.hitachi.com/rev/pdf/2005/r2005_01_103.pdf. [3] B. Singh, S. Gupta and B. Choo. US Patent 5,977,542, Date of Patent Nov. 2, 1999. [4] Y. Ose, M. Ezumi, T. Ishijima, H. Todokoro and K. Nagai. PROC. OF SPIE vo1.4689,2002 pp.128-137. [5] Qiang Zhang, Guogui Deng, Bin Xing, Jingan Hao, Qiang Wu and Yishi Lin, Study of CDSEM measurement issue caused by wafer charging, 2015 China Semiconductor Technology International Conference, DOI: 10.1109/CSTIC.2015.7153367, 2015. [6] W. K. Wong, J. T. L. Thong and J. C. H. Phang. IEEE Conference Publications, 1997, pp.97 - 102. [7] B. Choo, S. Punjabi, C. Morales, B. Singh, M. K. Templeton and M.P. Davidson. Proceedings of SPIE Vol, 2000, pp. 57-64. [8] S. Dupuis, T. Hayes, C. Archie and E. Solecky, Proceedings of SPlE, 2001, pp. 344-354. [9] Joren Severi, Gian F. Lorusso, Danilo De Simone, Alain Moussa, Mohamed Saib, Rutger Duflou and Stefan De Gendt, Chemically amplified resist CDSEM metrology exploration for high NA EUV lithography, Journal of Micro/Nanopatterning, Materials, and Metrology, 21(2), 021207, https://doi.org/10.1117/1.JMM.21.2.021207, (April 2022). [10] François Weisbuch, Jirka Schatz, Sylvio Mattick, Nivea Schuch, Thiago Figueiro, et al.. Investigating SEM-contour to CD-SEM matching. SPIE Advanced Lithography, Feb 2021, Online Only, France. ff10.1117/12.2583715ff. ffhal-03156583ff. [11] Brandon Ward and Lorena Page, Automated CD-SEM Recipe Generation Utilizing Design Pattern Layout, Hitachi High Technologies America, Inc. [12] H. Morokuma, A. Sugiyama, Y. Toyoda, W. Nagatomo, T. Sutani, R. Matsuoka, A New Matching Engine Between Design Layout and SEM Image of Semiconductor Device. (Hitachi High Technologies) 5752-53, SPIE 2005. [13] C. Tabery (AMD) and L. Page (Hitachi High Technologies), Use of Design Pattern Layout for Automatic Metrology Recipe Generation, 5752-173, SPIE 2005. [14] P. Cantu, G. Capetti (STMicroelectronics); R. Steffen, T. Sutani (Hitachi High Technologies), Evaluation of Hitachi CAD to CD-SEM Metrology Package for OPC Model Tuning and Product Devices OPC Verification, 5752-159, SPIE 2005. [15] Benjamin Bunday, Aron Cepler, Aaron Cordes, Abraham Arceo, CD-SEM metrology for sub-10nm width features, Proceedings Volume 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII; 90500T (2014) https://doi.org/10.1117/12.2047099. [16] Vaid, A., et al. A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM, Metrology, Inspection, and Process Control for Microlithography XXV, Proceedings of the SPIE, Volume 7971, pp. 797103-797103-20 (2011). [17] B. Bunday, T. Germer, V. Vartanian, A. Cordes, A. Cepler & C. Settens. “Gaps Analysis for CD Metrology Beyond the 22 nm Node,” Proc. SPIE, v8681, pp 86813B (2013). [18] E. Solecky, O. Patterson, A. Stamper, E. McLellan, R. Buengener, A. Vaid, C. Hartig, B. Bunday, A. Arceo, & A. Cepler, “Inline e-beam metrology: The end of an era for image-based critical dimensional metrology? New life for defect metrology (Invited Paper),” Proc. SPIE 8681, 86810D (2013). [19] Steigerwald, Michael. “A Mirror-Corrected Scanning Electron Microscope”, presentation from NIST Frontiers 2013, Gaithersburg, MD, March 2013. http://www.nist.gov/pml/div683/conference/2013_presentations.cfm . [20] Jennifer Church, Luciana Meli, Jing Guo, Martin Burkhardt, Chris A. Mack, Anuja De Silva, Karen E. Petrillo, Mary A. Breton, Ravi K. Bonam, Romain Lallement, Eric R. Miller, Brad Austin, Shravan Matham, Nelson M. Felix, Fundamental characterization of stochastic variation for improved single-expose extreme ultraviolet patterning at aggressive pitch, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 19, Issue 3, 034001 (July 2020). DOI: 10.1117/1.JMM.19.3.034001. |
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