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Buried gates in RCAT and BCAT are used to:
i) Mitigate the GIDL.
ii) Mitigate the parasitic capacitance of bit-line.
Figure 2413a shows the channel structure evolution of the cell transistor in dynamic random-access
memory, [5-8] including transmission electron microscope (TEM) images of RCAT, S-RCAT (sphere-shaped RCAT), and U-RCAT (U-shaped RCAT).
Figure 2413a. Channel structure evolution of the cell transistor in DRAM: Transmission electron microscope (TEM) images of (i) RCAT, (ii) S-RCAT, and
(iii) U-RCAT. (iv) (Middle) Schematic of a saddle-fin transistor with TEM cross-section images
of the (left) x- and (right) y-axes of the transistor. (v) Cross-sectional image of a buried word line
with a saddle-fin channel configuration. [9] |
Figure 2413b shows RCAT, BCAT and VCAT. In RCAT and BCAT technologies, the small word-line (WL) metal width is worsened by the non-scalable cell gate oxide thickness. Because VCAT would be free from lateral scaling, it can be one of the best ways to solve the problem.
 |
(a) |
(b) |
(c) |
Figure 2413b. (a) RCAT, (b) BCAT and (c) VCAT. [4]
The STEM images in Figure 2413c show the existence of a bridge defect connecting the gate contact to the
source contact in the indicated panel.
| Figure 2413c. STEM images showing the existence of a bridge defect connecting the gate contact to the
source contact in the indicated panel. [1] |
Figure 2413d shows a buried channel array
transistor (BCAT) in small cell size.
| Figure 2413d. Top view and cross-section TEM images of a buried channel array
transistor (BCAT). [2] |
Ideally,
gate materials in a BCAT have a uniform
depth. However, depths actually differ from each other because of process
variations, as shown in Figure 2413e, resulting in the leakage current distribution. The leakage current (i.e., GIDL) is exponentially proportional to the overlap length between drain node and gate edge (Lov). Figure 2413f shows the experimental results of the relationship between GIDL and Lov in a DRAM cell transistor.
| Figure 2413e. TEM images: (a) Process
variations shown by the double arrows, and (b) Overlap length, Lov, between drain node and gate edge. [3] |
Figure 2413f. Average GIDL increases exponentially with Lov. [3] |
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