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Figure 4183a shows a die, plane, block and page of NAND.

Hierarchical Structure in NAND Flash Memory:

• Cell:

  The basic unit of storage, holding a single bit of data (in SLC) or multiple bits (in MLC, TLC, QLC).

• Page:

  A collection of cells that form the smallest unit of data that can be written or read. Typically, a page might be 4 KB or 8 KB in size.

• Block:

  A larger unit that consists of multiple pages, typically ranging from 64 to 256 pages per block. It is the smallest unit that can be erased.

• Tile:

  A subsection of the NAND memory array. A tile typically includes several blocks and associated peripheral circuitry, such as wordline drivers and bitline multiplexers. Tiles are designed to optimize the efficiency and performance of the memory array.

• Plane:

  A larger organizational unit that includes multiple blocks. Typically, a NAND die is divided into multiple planes. Each plane can operate independently, which allows for parallelism and improved performance. For instance, a NAND die might have two or four planes.

• Cell → Page → Block → Plane:

  Cells are grouped into pages. Pages are grouped into blocks. Blocks are grouped into planes. Each plane contains multiple blocks and is capable of operating independently from other planes, allowing parallel operations.

In NAND flash memory, sub-blocks (sometimes referred to as sub-arrays or sub-sections) are separated for several reasons, primarily related to enhancing performance, improving reliability, and optimizing the manufacturing process. Sub-blocks contain multiple pages of memory cells and their associated peripheral circuitry, including components like page buffers, sense amplifiers, row and column decoders, and control logic.

Here are the main reasons of sub-blocks:

• Improved Parallelism and Performance:
  • Concurrent Operations: Separating the memory array into sub-blocks allows for concurrent read, write, and erase operations. This parallelism significantly enhances the overall performance of the NAND flash memory by allowing multiple operations to occur simultaneously across different sub-blocks.
  • Reduced Latency: By addressing smaller sub-blocks, the memory controller can manage data more efficiently, leading to reduced latency during data access.

• Enhanced Reliability and Endurance:
  • Wear Leveling: NAND flash memory cells degrade with each program/erase (P/E) cycle. By dividing the array into smaller sub-blocks, wear leveling algorithms can distribute the P/E cycles more evenly across the entire memory, enhancing the overall endurance of the NAND flash.
  • Error Correction: Smaller sub-blocks allow for more localized error correction, making it easier to detect and correct errors within specific areas of the memory array, thereby improving data integrity.

• Efficient Management of Bad Blocks:
  • Isolation of Defects: Defects in NAND flash memory can occur during manufacturing or operation. By organizing the memory into sub-blocks, it becomes easier to isolate and manage defective blocks. This improves the yield and reliability of the memory by allowing defective sub-blocks to be mapped out without affecting the entire memory array.

• Optimized Manufacturing Process:
  • Scalability: As NAND flash memory technology scales to higher densities and more complex 3D structures, organizing the memory into sub-blocks helps manage the complexity. It allows for more efficient use of die space and simplifies the design and manufacturing process.
  • Modularity: Sub-blocks provide a modular approach to designing NAND flash memory, enabling easier adaptation and customization for different applications and use cases.

• Power Management:
  • Selective Activation: By activating only the sub-blocks that are needed for a particular operation, power consumption can be reduced. This selective activation helps in managing power more efficiently, which is particularly important in mobile and embedded applications.

In advanced NAND flash memory architectures, sub-blocks typically have their own dedicated peripheral circuitry to manage operations such as reading, writing, and erasing data. This dedicated peripheral circuitry within sub-blocks enhances the efficiency and performance of the memory array.

Figure 4183b shows Cell array of 3D NAND flash memory.

Figure 4183b. Cell array of 3D NAND flash memory. [1]

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[1] https://technicalmasterblog.wordpress.com/2019/03/19/how-is-nand-flash-memory-array-organized/.
[2] Beomsu Kim and Myounggon Kang, Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory, Electronics 2022, 11, 2738. https://doi.org/10.3390/electronics11172738.