Electron microscopy
  
Open and Folded Bitline Array & Cells in DRAM
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Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix

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Figure 4206 shows the open and folded bitline array & cells in DRAM. A folded bitline sense-amplifier architecture is generally used in conventional DRAM.

Open (a) and folded (b) bitline array & cells in DRAM
(a)
Open (a) and folded (b) bitline array & cells in DRAM
(b)
Figure 4206. Open (a) and folded (b) bitline array & cells in DRAM. [1]

 

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[1] Bruce Jacob, Digital VLSI Design CMOS Memories and Systems, Part II, DRAM Circuits, 2004.

 

 

 
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