Electron microscopy
 
Poisson Yield Model (with Random-and-not-Clustered Defects/Fails)
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Early yield models in integrated circuit (ICs) fabrication have been based on the Poisson distribution, but these have turned out to be inadequate, underestimating the yield for large chips. [2]

If the distribution of the defects/fails is random, and not clustered, then Poisson model can be used. In this case, it can be assumed that the distribution of fails (faults) is random and the occurrence of a fail (fault) or at any location is independent of the occurrence of any other fault (fail). For a given µ, the fail probability that a die contains k defects is, [1]
         Poisson Yield Model ---------------------------------- [4305a]

Figure 4305 shows the plotted fail probability as a function of µ. Since the yield is equivalent to the probability that the chip contains no defects, the yield can be given by,
         Poisson Yield Model -------------------------------------- [4305b]
where,         
         D0 -- A constant defect density.

The fail probability as a function of µ

Figure 4305. The fail probability as a function of µ.

As an example, assuming a single IC chip has an average of 0.001 faults per die, if the Poisson yield model of Equation 4305b is applied, and the yield of a die with 500 of these ICs is equal to,
          e-500x0.001 = 60.7%
where,
         D0 = 0.001.
        Ac = 500.

Table 4305 shows estimated yield for 0 = 0.5, 1.0, 2.0, ∞ with different yield models.

Table 4305. Estimated yield for 0 = 0.5, 1.0, 2.0, ∞ with different yield models. [1]
Model α µ = 0.001
D0 = 0.001
Ac = 1   
µ = 0.5
D0 = 0.001
Ac = 500  
µ = 10
D0 = 0.001
Ac = 10000  
Negative Binomial 0.5 99.9% 70.7% 21.8%
1.0 99.9% 66.7% 9.1%
2.0 99.9% 64.0% 2.8%
Poisson 99.9% 60.7% 0.0%
Murphy -- 99.9% 61.9% 1.0%
Seed -- 99.9% 66.7% 9.1%

 

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[1] Way Kuo, Wei-Ting Kary Chien and Taeho Kim, Reliability, Yield, and Stress Burn-In: A Unified Approach for Microelectronics Systems Manufacturing & Software Development, 1998.
[2] J. A. Cunningham, “The use and evaluation of yield models in integrated circuit manufacturing,” IEEE Trans. Semiconduct. Manufact., vol. 3, pp. 60–71, May 1990.

 

 

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