TEG (testing element group)

TEG (Testing Element Group)
- Integrated Circuits and Materials -
- An Online Book -

Integrated Circuits and Materials http://www.globalsino.com/ICsAndMaterials/

Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix

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Figure 4360a shows a wafer.

Wafer

Figure 4360a. Wafer: ① Chip: The thin and small piece on the wafer where the electrical circuits are embedded. The IC chip; ② Scribe Line: The border between the chip without any electrical circuits. Lines to separate each chip on the wafer; ③ TEG (Test Element Group): A chip to test whether it works or not; ④ Edge Die: The damaged part. A bigger wafer has less damage than a wafer with a smaller diameter, which also reduces the loss factor; and ⑤ Flat Zone: The flat part to distinguish the round wafer structure. [1]

Figure 4360b shows TEG locations between dies.

TEG locations between dies

Figure 4360b. TEG locations between dies. [2]

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[1] https://semiconductor.samsung.com/us/support/tools-resources/dictionary/semiconductor-glossary-wafer/.
[2] https://www.disco.co.jp/eg/solution/library/laser/low_k.html.

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