Electron microscopy
  
Micron DRAM
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Figure 4660a shows that the array edge is sealed by a continuous trench of TiN plus top-plate material in a DRAM and the residual oxide
edge in the array from an isotropic etch through spacer cut-outs..

Edge of cell array in Micron 50-nm 1Gb SDRAM

Figure 4660a. Edge of cell array in Micron 50-nm 1Gb SDRAM. [1]

Figure 4660b shows another unusual feature with raised epitaxial source/drains in the RCATs.

Edge of cell array in Micron 50-nm 1Gb SDRAM

Figure 4660b. Recess-Channel-Array Transistors in Micron 50-nm 1Gb SDRAM: a) parallel to bitline b) parallel to wordline. [1]

Figure 4660c shows the capacitors in Micron 50-nm 1Gb SDRAM and Micron 30-nm SDRAM with voids at the center of the capacitors.

Edge of cell array in Micron 50-nm 1Gb SDRAM Edge of cell array in Micron 50-nm 1Gb SDRAM
(a)
(b)
Figure 4660c. (a) Capacitors in Micron 50-nm 1Gb SDRAM, and (b) Micron 30-nm DRAM. [1, 2]

 

TEM images of W/TiN buried wordlines in Elpida 33-nm DRAM TEM images of W/TiN buried wordlines in Elpida 33-nm DRAM
(a)
(b)
TEM images of W/TiN buried wordlines in Elpida 33-nm DRAM TEM images of W/TiN buried wordlines in Elpida 33-nm DRAM
(c)
(d)
Figure 4660d. Micron 30-nm 4-Gb DRAM: (a) parallel to wordline, (b) parallel to bitline, (c) plan-view at wordline level, (d) TEM image of Micron 30-nm DRAM metal 4 layer. [2]

 

 

 

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[1] Dick James, Recent Innovations in DRAM Manufacturing, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), DOI:10.1109/ASMC.2010.5551462, 2010.
[2] Dick James, Recent advances in memory technology, ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference, DOI: 10.1109/ASMC.2013.6552766, 2013.

 

 
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