Electron microscopy
  
Sidewall of STI
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Figure 4824a shows one type of STI MOS structures and several countermeasures for INCE of this structure. The lower Vth for the surface-channel STI MOSFET causes an increase in leakage current, and thus standby power. However, the leakage current is not as large as that inferred from INCE, due to its sharp cutoff characteristic. The methods a-c in Figure 4825b can suppress INCE. However, in those cases, the high gate controllability of STI MOSFET can be deteriorated as well.

One type of STI MOS structures and several countermeasures for INCE of this structure

Figure 4824a. One type of STI MOS structures and several countermeasures for INCE of this structure [8]: (a) Sidewall implantation [1,2], (b) Tapering the sidewall [3,4], (c) Rounding the corner edge [5], (d) Appropriate choice of the gate material [3, 6], and (e) Counter doping. [7]

 

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[1] Kurosawa K, Shibata T, Iizuka H, A new bird's beak free field isolation technology for VLSI devices. IEDM Tech Dig, 384, 1981.
[2] Shigyo N, Dang R, Analysis of anomalous subthreshold current in a fully recessed oxide MOSFET using a three-dimensional device simulator. IEEE Trans Electron Devices, ED-32, 441, 1985.
[3] Shigyo N, Three-dimensional Simulation of VLSI Devices, PhD thesis, Tohoku University, 1988.
[4] Shigyo N, Konaka M, Dang R, Three-dimensional simulation program for MOS devices and its application to the analyis of the narrow-channel effect. Trans IEICE, J66-C, 1035, 1983.
[5] Chang C. P., et al, A highly manufacturable corner rounding solution for 0.18 um shallow trench isolation, IEDM Tech Dig, 380, 1997.
[6] Shigyo N, et al, Three-dimensional analysis of subthreshold swing and transconductance for a fully recessed oxide (trench) isolated 1/4-um-width MOSFET's, IEEE Trans Electron Devices, ED-35, 945, 1988.
[7] Ohe K, et al. Narrow-width effects of shallow trench-isolated CMOS with n+-silicon gate, IEEE Trans Electron Devices, ED-36, 1110, 1989.
[8] Naoyuki Shigyo and Takayuki Hiraoka, A review of narrow-channel eects for STI MOSFET's: A difference between surface- and buried-channel cases, Solid-State Electronics 43, 2061-2066, (1999).








 

 

 

 
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