Fab Flow and Properties (e.g. Leakage Current) of Shallow Trench Isolation (STI)
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The critical applications of plasma etching technologies are: [12]
          i) Form precisely controlled profiles of high-aspect-ratio contacts (HARC).
          ii) Form gate stacks.
          iii) Form shallow trench isolation (STI) in the front end of line (FEOL).
          iv) Form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL).

Table 4834a. Fab flow and properties (e.g. leakage current) of shallow trench isolation (STI). The starred and bold-items are the key development of specific process.

  Process Hardmask                                           Critical problems  
Flow Substrate Pad oxidationa Other layer b Resist mask with active layer/dummy STI photod SiN etchinge Pad oxide etchingf Resist removalh Si trench etchingg Undercut of pad oxidei Linear oxidationj SiN recess Gap fill with oxide depk Densification of trench oxideo Photomask open in wide active area SiO2 etching Resist removal CMP planarizationc Pad nitride stripl Well implantm Pad oxide strip Sacrificial oxidationn Multigate oxidation HF Gate electrode formation   Reference
Conventional STI p Si with a resistivity 5~10 Ωcm 11 nm in a dry O2 ambient at 950 °C Pad nitride = 190 nm at 785 °C Yes   Yes Yes   STI depth = 300nm with Cl2 + O2   15 nm   500 nm TEOS Annealed
in a N2 ambient for 1 hour because the pad-oxide striper
(HF) can etch TEOS excessively		       Yes H3PO4, 160 °C,
and 1 hr		   Yes         [10]
DRAM   Buffer oxide PolySi                                             [11]
DRAM p Si 15 nm Pad nitride = 200 nm Yes*   Dry etching   Yes 400 nm   20 nm gate-oxide in 1000 °C HCl+O2 arnbient By hot
phosphoric acid for embedded logic process (to avoid dip)*		 600 nm HDP CVD to fill the gap, and densified at 1000 °C for 30 min in N2 anrbient.   Yes Yes Yes Dry-etch-assisted CMP under high selectivity
(SiO2/SiN)		 Yes     20 nm after HF: 15 nm 22nm@ DRAM; 28nm @Logic Yes   [1]
                                                     
                                                     
                                                     
                                                     
       



                                           
                                                     
                                                     
                                                     
                                                     

a. Pad oxidation is used to prevent stresses by pad nitride. If pad nitride is deposited directly on bare silicon, then nitride stress can cause defect in silicon substrate. The pad oxide layer has relatively lower stress than LOCOS, lower thickness than LOCOS.
b. Pad nitride layer is used as hard mask for trench etching and used as a CMP polish-stop-layer for planarization after trench fill by CVD oxide.
c. The pad nitride laser is a CMP polish-stop-layer.
d. STI field area will be open.
e. Anisotropically etched using plasma etching process.
f. Anisotropically etched using plasma etching process.
g. Si trench etching uses plasma etching. The goals of this etch process are: i) Correct depth without etch stop layer (timing the etch for certina depth), ii) get desired sidewall slope (more vertical), iii) With rounded bottom corner, and iv) Smooth sidewall and minimum Si damage.
h. Photoresist can be stripped before or after trench etching.
i. Undercut of pad oxide with HF dip or isotropic dry etching surface treatment process are used after trench formation, in order to make the rounding of the top corner of the recessed channel region during liner oxidation, so that Si damaged by the earlier etching process and some of the sidewall Si are removed. (Figure 4834c)
j. Role of liner oxide are: i) Remove residual damage caused by plasma etch process, ii) Passivate Si surface of trench to provide stable interface between Si and trench fill oxide for higher threshold voltage of parasitic field transistor, lower leakage current, and iii) To corner rounding of active region because the top corner is a sharp corner after trench etch. (Figure 4834c)
k. Gap fill of trench by CVD oxide deposition: LPCVD TEOS, APCVD, HDP CVD oxide can be used to deposit oxide without void. Densification is need to make less field loss during wet etch and cleaning step. Reverse active photo and RIE etch can be used.
l. Nitride strip can be done by: i) HF + hot phosphoric acid, ii) HF step is to remove oxynitride layer grown during liner oxidation, iii) Using wet process for nitride removal (inexpensive and high selectivity than dry etch, and need to remove backside nitride deposited during pad nitride deposition). This nitride removal enables the integration of the RCATs with planar transistors outside of the array, as the hard mask is removed in peripheral regions during the trench etching process, allowing two gate oxides while using a single gate definition lithography step.
m. The remained pad oxide is used as buffer oxide for well implant.
n. Strip remained pad oxide and grow sacrificial oxide as buffer oxide for implantation.
o. Trench oxide can be densified in O2 ambient, then O2 react with residual H2 in trench oxide or nitride film and form H2O. However, this can cause Kooi effect.

 

Table 4834b. xx.

     
     
     
     
     

 

For STI, the critical issue in the case of the DRAM embedded logic process is that a higher step height at STI occurs between the DRAM and logic regions due to the difference in the CMP rate between SiO2 and SiN, which arises from the difference in the active area (AA) density. On the other hand, it is necessary to ensure against silicon erosion and polysilicon residue by gate electrode formation. In particular, a dual work function gate is indispensable for high-performance logic, it is difficult to form
P+ and N+ gates. Moreover, it is used to obtain two different gate-oxide thicknesses in the DRAM region and high-performance logic region. To remove the first gate-oxide layer in the logic region, the dip is amplified at the STI top corner by HF solution. The dip leads to the undesirable double hump in the subthreshold IV characteristic and a reverse narrow channel effect (RNCE) [2, 3]. To prevent the dip, several approaches of varying complexity have been proposed:
         i) T-shaped STI. [3]
         ii) Sidewall protection. [5,6]
         iii) Mini-LOCOS oxidation. [7,8]
         iv) SiN recess for the DRAM embedded logic process (Figure 4834a). [9]

conventional STI, and (b) proposed STI which SN lateral etch = 54 nm conventional STI, and (b) proposed STI which SN lateral etch = 54 nm
(a)
(b)

Figure 4834a. SEM cross-sectional view: (a) conventional STI, and (b) proposed STI which SiN lateral etch = 54 nm. [9]

Process flow of the conventional STI process

Figure 4834b. Process flow of the conventional STI process. [10]

Process flow of the conventional STI process

Figure 4834c. (a) Pad oxide undercut and (b) Liner oxidation.

 

 

 

 


[1] T. Yamazaki, K. Ohno, N. Tsuchiya and T. Gocho, Optimized Shallow Trench .Isolation Technology for DRAM Embedded Logic process, 1999 Intcrnstional conf.rmce on solial state Devices a l Metelials, Tokyo, pp. l8-19, (1999).
[2] Andres Bryant et.al., IEEE Electron Dev.(l993) p.412.
[3] A.H.Perera elal., IEDM (1995) p. 679.
[4] T.lshijima et al., IEDM (I 990) p. 257.
[5] PieneC. Fazanetal., IEDM (1993) p. 57.
[6] W.K.Yeh etal., SSDM (1998) p. 98.
[7] A.Chatterjee et al., IEDM, (1996) p. 826.
[8] T. Parftetal., IEDM, (1994), p.67
[9] T. Yamazaki, K. Ohno, N. Tsuchiya and T. Gocho, Optimized Shallow Trench .Isolation Technology for DRAM Embedded Logic process, 1999 Intcrnstional conf.rmce on solial state Devices a l Metelials, Tokyo, pp. l8-19, (1999).
[10] In Man Kang, Hyuck In Kwon, Myung Won Lee, Byung-Gook Park, Jong Duk Lee, Sang Sik Park, Jung Chak Ahn and Yong Hee Lee, Characteristics of Conventional STI Process-Related
Deep-Level Traps in Silicon, Journal of the Korean Physical Society, 44(1), pp. 69∼72, 2004.
[11] Kim, J.Y., et al., “The Breakthrough in data retention time of DRAM using Recess-Channel-Array_Transistor (RCAT) for 88nm feature size and beyond”, 2003.
[12] Haruhiko ABE, Masahiro YONEDA, and Nobuo FUJIWARA, Developments of Plasma Etching Technology for Fabricating Semiconductor Devices, Japanese Journal of Applied Physics, Vol. 47, No. 3, 2008, pp. 1435–1455.

 

 

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