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Row Hammer is a serious security threat to the modern computing systems using DRAM as main memory. [1] It causes charge loss in the DRAM cells adjacent to a frequently activated aggressor row and eventually leads to data bit flips in those cells.
| Scaling down the access device to provide higher data storage ability in the same
size memory chip by increasing the device density |
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Conventional plenary access devices cannot be used in sub-50 nm technology due to unacceptable leakage from the short channel effect (SCE) [2, 3] |
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A three-dimensional (3D) device structure of a recess channel with an extended distance between source and drain is used to minimize the leakage issues [4,5] |
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A fin-curved gate area, which is called a saddle-fin (S-Fin) device, is designed in the recess channel to maintain the current drivability [6, 7] |
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A buried word line (WL) of the access device is used to provide a smaller step height difference for better yield of cell capacity during fabrication [8] |
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The unit area of the DRAM
cell shrinks from 6 F2 to 4 F2, leading a smaller
spacing between access devices and a stronger coupling effect between
neighboring transistors and word lines [9, 10] |
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A coupling effect could introduce an electromagnetic
coupling force between cells and increase the sub-threshold leakage
current [11, 12] |
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The behavior of the increase of leakage in the
access devices of adjacent rows (victim rows) by frequent activation
on a given row is called row hammering [13] |
Figure 4839. Origin of row hammering in DRAM technology. [14]
Proposed solutions of row hammering are:
i) Reducing the row hammer effect via fabrication process optimization by an additional phosphorus (P) implantation with energy and dosage modification applied in the
common source area between two adjacent buried word lines of the access devices and energy adjustment of the well implantation are applied to provide a doping profile modification in the array device. [14]
As shown in Figure 4839, row Hammer is a type of vulnerability in DRAM memory where repeatedly accessing (hammering) a row of memory can cause bit flips in adjacent rows. This occurs because of the physical interference and electrical disturbance caused by the high-frequency access to the rows. Mechanism: - Repeated Access: When a row of memory cells is accessed repeatedly and rapidly, it can induce charge leakage in adjacent rows.
- Bit Flips: The electrical disturbance can cause bits in these adjacent rows to change state, flipping from 0 to 1 or vice versa.
- Vulnerability: This bit flipping can lead to data corruption, potentially causing software errors, crashes, or security vulnerabilities.
Impact on Error Correction: - Error Correction Codes (ECC) is designed to detect and correct a certain number of bit errors in memory.
- However, the Row Hammer effect can induce multiple bit flips across different rows and even different memory modules (DIMMs), which can overwhelm ECC capabilities.
| Figure 4839. Row hammer attach can flip many bits in multiple DRAMs, easily overwhelming error correction capabilities.[15] |
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[1] Yeonhong Park, Woosuk Kwon, Eojin Lee, Tae Jun Ham, Jung Ho Ahn, Jae W. Lee, Graphene: Strong yet Lightweight Row Hammer Protection, 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), DOI 10.1109/MICRO50266.2020.00014, 2020.
[2] J. V. Kim et al., “S-RCAT (sphere-shaped-recess-channel-array transistor)
technology for 70 nm DRAM feature size and beyond,” in Proc. VLSI
Symp. Tech. Dig., Jun. 2005, pp. 34–35.
[3] S. Hong, “Memory technology trend and future challenges,” in Proc.
IEDM Tech. Dig., Dec. 2010, pp. 12.4.1–12.4.4.
[4] J. Y. Kim, C. S. Lee, S. E. Kim, and I. B. Chung, “The breakthrough
in data retention time of DRAM using recess-channel-array transistor
(RCAT) for 88 nm feature size and beyond,” in Proc. VLSI Symp. Tech
Dig., Jun. 2003, pp. 11–12.
[5] M. J. Lee et al., “A comparative study of the DRAM leakage mechanism for planar and recessed channel MOSFETs,” Solid-State Electron., vol. 53, no. 9, pp. 998–1000, Sep. 2009.
[6] S.-W. Chung et al., “Highly scalable saddle-fin (S-Fin) transistor for sub
50 nm DRAM technology,” in Proc. VLSI Symp. Tech. Dig., Jun. 2006,
pp. 147–148.
[7] S.-W. Ryu, M. Yoo, D. Choi, S. Cha, and J.-G. Jeong, “Data retention characteristic for gate oxide schemes in sub-50 nm saddle-fin transistor dynamic-random-access-memory technology,” Jpn. J. Appl. Phys., vol. 50, Apr. 2011.
[8] T. Schloesser et al., “A 6 F2 buried wordline DRAM cell for 40 nm and
beyond,” in Proc. IEDM Tech. Dig., Jan. 2009, pp. 1–4.
[9] J.-T. Lin, P.-H. Lin, S. W. Haga, Y.-C. Wang, and D.-R. Lu, “Transient
and thermal analysis on disturbance immunity for 4 F2 surrounding gate 1
T-DRAM with wide trenched body,” IEEE Trans. Electron Devices,
vol. 62, no. 1, pp. 61–68, Jan. 2015.
[10] K.-W. Song et al., “A 31 ns random cycle VCAT-based 4 F2 DRAM
with manufacturability and enhanced cell efficiency,” IEEE J. Solid-State
Circuits, vol. 45, no. 4, pp. 880–887, Apr. 2010.
[11] M. J. Lee et al., “A proposal on an optimized device structure with experimental studies on recent devices for the DRAM cell transistor,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3325–3335, Dec. 2007.
[12] D. H. Kim, P. J. Nair, and M. K. Qureshi, “Architectural support for
mitigating row hammering in DRAM memories,” IEEE Comput. Archit.
Lett., vol. 14, no. 1, pp. 9–12, Jan. 2015.
[13] [12] K. Park, S. Baeg, S. J. Wen, and R. Wong, “Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3× nm technology,” in Proc. IEEE Int. Rel. Workshop Final Rep., Oct. 2014,
pp. 82–85.
[14] Chia-Ming Yang, Chen-Kang Wei, Yu Jing Chang, Tieh-Chiang Wu, Hsiu-Pin Chen, and Chao-Sung Lai, Suppression of Row Hammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology, IEEE Transactions on Device and Materials Reliability, 16, (4), 685, 2016.
[15] Source: Rambus.
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