Figure 4882a shows that main-word-lines (MWL0, MWL0B) driven by row decoders is laid out in a two or four times pitch as sub-word-lines. The row decoder and the word-drive decoder include CMOS output gates for the stable operation of main and sub word-lines. Boosted voltage (V_BOOT) is supplied to not only word drive decoders but also row decoders to charge the gate of the sub-word-drive-transistor enough to realize the fast decoding even with the small sub-word-drive-transistor. By integrating the decoding circuit and the voltage converter to transform the lower voltage signals into the boosted voltage level. Only the output gate of the word-reset signal-line (MWLOB) is driven at the external voltage (V_CC) instead of VBOOT for reduction of the power dissipation.

Figure 4882b shows the schematics of a typical power supply of DRAM. There are three voltage levels:
         i) the external voltage (V_CC) supplied to most of the peripheral circuits,
         ii) the internal limited voltage (V_LIM) supplied to the sense amplifiers,
         iii) the internal boosted voltage (V_BOOT) supplied to the row decoders and the word-drive decoders.

[1] K. Noda， T. Saeki, A. Tsujimoto, T. Murotani, and K. Koyama, "A boosted dual word-line decoding scheme for 256 Mb DRAMs," in 1992 Symposium on VLSI Circuits Digest ofTechnical Papers, pp. 112-113.