Figure 4886a shows functional diagrams of DRAM. Here,
          C₁ - C₅ and R₁ - R₅ -- 10 address inputs. Each of them is connected to an on-chip address input buffer.
          Input buffers -- Drive the row (R) and co/umn (C) decoders, which have two purposes:
                                  i) to provide a known input capacitance (C_IN) on the address input pins,
                                  ii) to detect the input address signal at a known level so as to reduce timing errors.
          R/W* -- an input.
          CE* -- can be low or high.

Figure 4886a. Functional diagrams of DRAM. [1]

[1] Brent Keeth, R. Jacob Baker, Brian Johnson, and Feng Lin, DRAM Circuit Design: Fundamental and High-Speed Topics, (2007).