Electron microscopy
  
tRC (Refresh Cycle Time)
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A DRAM cell is composed of an access transistor and one leaky capacitor. [2] To prevent data loss due to leakage, DRAM cells require recharge periodically. These recharge operations are also known as DRAM refresh. Two important parameters for DRAM refresh are:
          i) Refresh interval or refresh time (tREF).
          ii) Refresh cycle time (tRFC), which is the time interval between Refresh and Activation commands.

Refresh commands are issued by memory controller typically every 7.8μs to refresh a bin, which is composed of multiple rows. That is, the memory controller sends a refresh command to DRAM devices every tREF (7.8 µs normally), and the duration of a refresh command is referred to as tRFC, which means that the refresh operation takes tRFC to complete, which proportionally depends on the number of rows in the bin. The refresh overhead is given by tRFC/tREF, which is the ratio of refresh time to refresh all its cells. Upon receiving REF, DRAM device refresh the designated rows tracked by the internal counter. The whole memory rank is typically refreshed every 64 ms, the vast majority cells can hold data for a much longer time.

Table 4937a. Refresh cycle time (tRFC) and refresh overhead (tRFC/tREF) among different density. [2]

Density tRFC tREF tRFC/tREF
1 Gb 110 ns 7.8 µs 1.54%
2 Gb 160 ns 7.8 µs 2.25%
4 Gb 260 ns 7.8 µs 3.65%
8 Gb 350 ns 7.8 µs 4.91%
16 Gb 530 ns 7.8 µs 7.44%
32 Gb 890 ns 7.8 µs 12.49%

 

All-banks-concurrent row refresh timing

Figure 4937. All-banks-concurrent row refresh timing. [1]

Table 4937b. Refresh cycle times for DDR and DDR2 SDRAM devices. [1]

Refresh cycle times for DDR and DDR2 SDRAM devices

Table 4937c. External DRAM controller parameters on DRAM board. [3]

Parameter Description (unit)
Write buffer size Number of write queue entries
Read buffer size Number of read queue entries
Write high/low threshold High/low watermark for write queue
Scheduling policy FCFS or FR-FCFS
Address mapping RoRaBaCoCh, RoRaBaChCo, RoCoRaBaCh [3]
Page policy Open or closed (adaptive or not)
Frontend latency Static frontend latency (ns)
Backend latency Static backend latency (ns)
Device bus width Data bus with per DRAM device (bits)
Burst length DRAM burst length (beats)
Row-buffer size Device row buffer size (bytes)
Devices per rank -  
Ranks per channel -  
Banks per rank -  
Channels Channel count for the address decoding
tRCD Row to column delay (ns)
tRAS Row access strobe (ns)
tRP Row precharge time (ns)
tCL Column access latency (ns)
tBURST Burst duration (ns)
tRFC Refresh cycle time (ns)
tREFI Refresh command interval (ns)
tWTR Write to read switching time (ns)
tRRD Row to row activation delay (ns)
tXAW Activation window (ns)
Activation limit Number of activates in window

 

 

 

 

 

 

 

 

[1] Bruce Jacob, Spencer W. Ng, and David T. Wang, Memory Systems: Cache, DRAM, Disk, 2008.
[2] Wei-Kai Cheng, Po-Yuan Shen and Xin-Lun Li, Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency, Micromachines, 10, 590, (2019).
[3] Andreas Hansson; Neha Agarwal; Aasheesh Kolli; Thomas Wenisch; Aniruddha N. Udipi, Simulating DRAM controllers for future system architecture exploration, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), DOI: 10.1109/ISPASS.2014.6844484, (2014).

 
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