Column Decoders (CDECs/CDs)

Column Decoders (CDECs/CDs)
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Figure 4978a shows the data transfer from CPU to DRAM memory in a computer.

Data transfer from CPU to DRAM memory in a computer

Figure 4978a. Data transfer from CPU to DRAM memory in a computer, including an external memory controller. [4]

Employing a smaller array will improve the performance; however, the overhead of WL drivers (WLDVs), column decoders (CDECs), and the sense amplifiers (SAs) will also be increased [1].

Structure of DRAM and peripheral circuitry

Figure 4978b. Structure of DRAM and peripheral circuitry. [3]

Table 4978a. Main differences of the two circuits.

	Circuit in Figure 4978c (a)	Circuit in Figure 4978c (b)
Sensing scheme	Voltage sensing using a passive load	Complementary current sensing
S/N	Lower	Higher
Speed (see Figure 4978d (d))	Slower	Faster
Data-line pitch		Doubled
Interference noise		Is minimized by shielded data-line architecture as well as the data-line shielded memory cell
Scheme	Voltage sensing	Complementary current sensing
Problems that degrade sensing speed	A CD switch must be turned on after the establishment of a sufficiently large voltage difference between a pair of data lines. Otherwise, the readout information is destroyed by the current flowing from the I/O lines, due to small data-line capacitance compared with the I/O line’s parasitic capacitance
Problems that degrade sensing speed	The sense amplifier has to charge the I/O line’s capacitance up to about 200 mV, which is required by the next stage (main) amplifier. The delay time for charging this capacitance increases as the operating voltage decreases.	High speed because the CD switch can be turned on before a large voltage difference is established between a pair of data lines
Advantages		Employ separated readout and write-in gates instead of a common I/O gate
Advantages		By separating the data line from the readout line, the CD switch can be turned on before a large voltage difference is established between a pair of data lines
Chip size		Increases by 3%
Readout MOS	NMOS	NMOS

Figure 4978c shows the schematic diagrams of two different sense circuits. Table 4978 lists the main differences of the two circuits. In the design in Figure 4978c (b), the voltage swing of the common RO lines is as low as 20 mV, and thus the charging time of the RO line’s parasitic capacitance, C_RO, is reduced by one order of magnitude, and then the transmission delay is improved considerably.

Schematic diagrams of sense circuits

Figure 4978c. Schematic diagrams of sense circuits: (a) conventional voltage sensing scheme, and (b) new complementary current sensing scheme. CD = column decode, WI = write-in, RO = readout. Adapted from [5]

Table 4978b. Main differences of the different current sense circuits in Figure 4978d.

Scheme	Common-base current sensing	NMOS feedback current sensing	Complementary current sensing
Special design	Bipolar transistor Ql		The signal path consists of an NMOS readout gate M3 and PMOS drive transistor M2 with feedback.
Speed (see Figure 4978d (d))	Fastest
Disadvantages [5]	Does not operate when V_CC is less than 2.5 V	A minimum operating voltage is 1.9 V so that 1.5-V operation cannot be achieved	High-speed operation with a supply voltage as low as 1.25 V
Diagram	Figure 4978d (a)	Figure 4978d (b)	Figure 4978d (c)
Minimum operating voltage (V_T)	V_RO + V_CE + V_S + V_B	V_RO + V_T + V_S	V_T + V_S
			Lowest
	V_RO: the voltage level of the RO lines; V_S: the dynamic range for the sense signal
	I_B: the bias current which is needed for both RO and lines to minimize the voltage swing on the RO lines; V_B: the voltage drop across a load resistance induced by this bias current.
Applications	BiCMOS DRAM [6]	16-Mb DRAM presented at the 1988 ISSCC [7]	The sense circuit in Figure 4978c (b)

Figure 4978d. Different current sense circuits: (a) Common-base sensing scheme, (b) NMOS-driven current sensing scheme, (c) PMOS-driven current sensing scheme, and (d) Simulated sense delay for several sensing schemes. Assuming V_RO = V_CC/2. COMPL. = Complementary. Adapted from [5]

Figure 4978d shows functional diagrams of DRAM. Here,
          C₁ - C₅ and R₁ - R₅ -- 10 address inputs. Each of them is connected to an on-chip address input buffer.
          Input buffers -- Drive the row (R) and column (C) decoders, which have two purposes:
                                  i) to provide a known input capacitance (C_IN) on the address input pins,
                                  ii) to detect the input address signal at a known level so as to reduce timing errors.
          R/W* -- an input.
          CE* -- can be low or high.

Functional diagrams of DRAM

Figure 4978d. Functional diagrams of DRAM. [2]

[1] T. Kimuta, K. Takeda, Y. Aimoto, N. Nakamura, T. Iwasaki, Y. Nakazawa, H. Toyoshima, M. Hamada, M. Togo, H. Nobusawa, T. Tanigawa, 64 Mb 6.8 ns random ROW access DRAM macro for ASICs, ISSCC, Dig. Tech. Papers, Feb 1999, pp. 416–417.
[2] Brent Keeth, R. Jacob Baker, Brian Johnson, and Feng Lin, DRAM Circuit Design: Fundamental and High-Speed Topics, (2007).
[3] https://blog.naver.com/minky0118/221860772321.
[4] www.cnblogs.com/.
[5] Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto and T. Kisu, An experimental 1.5-V 64-Mb DRAM, IEEE Journal of Solid-State Circuits, 26(4), pp. 465 - 472, 1991.
[6] G. Kitsukawa et al., “A 23-ns 1-Mb BiCMOS DRAM,” IEEE J. Solid-state Circuits, vol. 25, pp. 1102-1111, Oct. 1990.
[7] M. Aoki et al., “An experimental 16Mb DRAM with a transposed data-line structure,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 250-251.

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