Integrated Circuits and Materials

In Figure 0132a, the cross-sectional structure of the stacked backside-illuminated (BSI) pixel array is presented. The upper layer contains the micro lens (ML), color filter array (CFA), and deep photodiode (PD), which are responsible for capturing and processing incoming light. The lower layer contains the sample-and-hold (S/H) capacitors and the readout circuit, which are dedicated to storing and processing the electrical signals generated by the photodiodes. These two layers are connected by pixel-level hybrid bumps (HB), enabling effective signal transfer between the photodiode layer and the readout circuitry. This arrangement maximizes photon detection on the top layer while keeping the storage and readout components shielded on the bottom, contributing to low parasitic light sensitivity (PLS) and high optical performance

[1] Ken Miyauchi, Kazuya Mori, Toshinori Otaka, Toshiyuki Isozaki, Naoto Yasuda, Alex Tsai, Yusuke Sawai, Hideki Owada, Isao Takayanagi and Junichi Nakamura, A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel, Sensors, 20(2), 486, 2020.