Integrated Circuits and Materials

An Online Book, First Edition by Dr. Yougui Liao (2018)

Practical Electron Microscopy and Database - An Online Book

Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix

Notch Defect in ICs

Figure 0139 (a) shows a TEM cross-section of a failing transistor, which reveals a poly notch located at the bottom left corner of the gate electrode. This defect explains the asymmetrical electrical behavior observed in the transistor. Figure 0139 (b) provides probe data that correlates with the asymmetrical behavior observed in the transistor. The poly notch defect causes weak inversion or even depletion under low gate voltages, which leads to an imbalance between the left and right driver transistors. This combination of probe data and TEM analysis confirms that the poly notch is responsible for the failure mechanism.​ "Additional resistance" in Figure 0139 (b) indicates extra resistance observed beyond the expected channel resistance (Rch). In this case, it suggests that an unexpected resistance due to a defect in the transistor, which is the poly notch. This defect creates electrical irregularities, which cause increased or unbalanced resistance in the transistor, affecting its performance. The channel resistance (Rch) of the transistor is the inherent resistance of the channel region between the source and drain, which is normally part of the transistor's operational parameters. Rch influences how easily current flows through the channel when a voltage is applied between the source and drain. 

TEM cross section of a failing transistor showing a poly notch at the left bottom corner
TEM cross section of a failing transistor showing a poly notch at the left bottom corner
(a)
(b)

Figure 0139. (a) TEM cross section of a failing transistor showing a poly notch at the left bottom corner, and (b) Poly notch causing weak inversion or even in depletion under low gate voltages. [1]

 

 

 

 

 

 

 

 

[1] Larry Liu, Yuguo Wang, Hal Edwards, David Sekel, Dan Corum, Combination of SCM/SSRM Analysis and Nanoprobing Technique for Soft Single Bit Failure Analysis, Proc. 30th International Symposium for Testing and Failure Analysis, Worcester, 2004.