Integrated Circuits and Materials

Figure 0181 shows the equivalent circuit model for cell delay in SRAM. In this model, the cell transistors play a critical role in discharging the total bit-line capacitance, which is crucial for determining the delay characteristics within memory arrays. The model emphasizes that optimizing cell delay is challenging without reducing the number of rows in the array, as the cell transistors are typically minimized in size to enhance density. The row decoder is responsible for activating the appropriate word-line associated with the selected row. This operation is critical because enabling the word-line allows access transistors within each cell in that row to connect the cell to the bit-lines. The row decoder achieves this by receiving address inputs, decoding them, and generating the correct word-line signal while ensuring all other word-lines remain inactive. This process is essential to ensure only the cells in the desired row are accessed, avoiding interference with other data stored in the memory array.

[1] Karim Abbas, Handbook of Digital CMOS Technology, Circuits, and Systems, 2020.