Integrated Circuits and Materials

Figure 0182a shows the equivalent circuit model for cell delay in SRAM. In this model, the cell transistors play a critical role in discharging the total bit-line capacitance, which is crucial for determining the delay characteristics within memory arrays. The model emphasizes that optimizing cell delay is challenging without reducing the number of rows in the array, as the cell transistors are typically minimized in size to enhance density. The sense amplifier shown in Figure 0182b in the SRAM operates to accelerate the read process by amplifying the differential signal developed between the bit-lines (BL and BLB). During a read operation, the bit-lines are first precharged and then connected to the sense amplifier, which detects the small voltage difference between BL and BLB caused by the accessed cell's state. The sense amplifier then quickly drives this differential signal to full logic levels, allowing rapid and accurate readout. This design is especially important because SRAM cells may not establish a full voltage swing on their own due to their minimal size and low driving capability.

In SRAM arrays, each bit-line pair (BL and BLBar) is configured as a differential pair to enhance noise immunity and signal clarity, with a single sense amplifier typically allocated per column. During a read operation, the bit-lines are initially precharged to a common intermediate voltage before accessing any cell. This precharge process, however, can be relatively slow due to the limited drive strength of the minimized transistors within each cell, which are designed for high density rather than speed. Once the cell is accessed, a small differential voltage develops between BL and BLBar, reflecting the stored data. At this stage, the sense amplifier plays a critical role, not by accelerating the precharge itself, but by rapidly detecting and amplifying this small differential signal to drive it to a full logic level. This amplification significantly accelerates the read access time, overcoming the limitations of the cell’s low drive capability. Therefore, while the sense amplifier does not directly impact the precharge phase, it is essential for achieving fast and accurate read operations in high-density SRAM arrays by amplifying the differential bit-line signals.

In Figure 0182b, for reading, Nc needs to be in saturation region since it acts as a current source. M1 and M2 also need to be in saturation region. On the other hand, M4 also needs to be on.

[1] Karim Abbas, Handbook of Digital CMOS Technology, Circuits, and Systems, 2020.