Integrated Circuits and Materials

Memory Built-In Self-Test (MBIST) is hardware built into chips to test memory elements automatically without requiring external ATE. It’s optimized for fast production testing, designed to quickly identify faults during manufacturing. It is traditionally employed to test memory arrays by generating a pass/fail output for each test. However, these tests typically do not provide detailed information about the exact nature or location of the fault. In this case, custom MBIST patterns can be used to enhance fault localization. These patterns include the logical unload sequence from targeted addresses, allowing the comparison vector to match the failing signature from defective units. When the test result matches the expected failure signature, a fault is successfully isolated and localized using LIFA (Logic Information for Fault Analysis). [1] LIFA refers to a method of providing more detailed diagnostic information for fault localization during the test process. LIFA helps in isolating faults by matching failure signatures and providing insights into the type or location of defects, which is crucial for debugging and failure analysis in semiconductor manufacturing.

The MBIST architecture, as shown in Figure 0652, involves an embedded testing engine responsible for evaluating memory components within a System on Chip (SoC) without requiring external communication. The MBIST system includes a BIST (Built-In Self-Test) engine (controller) that generates both the test patterns and control signals for the memory under test. The BIST engine manages the read and write operations, where it generates addresses and input data for write operations and expected output data for read operations. A comparator checks if the actual memory output matches the expected value, and if there is a discrepancy, the system flags a failure. The multiplexer (MUX) selects between normal mode and test mode based on the test signal, ensuring that the MBIST can operate independently of the system's regular function. The architecture is designed to identify memory faults like stuck-at faults while reducing power consumption by minimizing switching activities during the testing phase

Figure 0652. MBIST architecture. [2]

MBIST diagnostics for single-bit failures usually don’t need EFI. However, multiple-bit, column, row, or controller failures typically require EFI to pinpoint the faulty controller logic. MBIST failures typically require running the test pattern in a loop due to its built-in self-test mode.

For SRAM, MBIST refers to an embedded test mechanism used in SRAM to identify defects by generating a fail bit map. [3] This map enables engineers to pinpoint the defect's position by mapping logic bit addresses to their physical locations on the chip. Through MBIST, failure localization becomes more efficient, helping diagnose common SRAM issues such as single cell fail (SCF), cluster fail (CF), and bit or word line oriented fails (BLF/WLF). It serves as a critical tool for identifying and analyzing yield-impacting defects, especially in process-sensitive SRAM designs.

[1] Keith A. Serrels, Kris Dickson, Clifford Howard, Jose Garcia, Eric Foote, Gary Clark, Ben Gonzalez, and Chinemerem Nwokolo, On Demand Bit-Level SRAM Validation using CW 785nm Laser-Induced Fault Analysis (LIFA), ISTFA 2023: Proceedings of the 49th International Symposium for Testing and Failure Analysis Conference, 2023.
[2] Nor Z.Haron, Siti A.Junos, Abdul Hadi A.Razak, and Mohd Y.Idris, “Modeling and Simulation of Finite State Machine Memory Built-in Self Test Architecture for Embedded Memories”, Asia-Pacific Conference On Applied Electromagnetics”, 2007.
[3] Zhongling Qian, Frank Siegelin, Birgit Tippelt, Stefan Müller, Localization and physical analysis of a complex SRAM failure in 90nm Technology, Microelectronics Reliability, 46, 1558–1562, 2006.