Isolation Transistor Between Bitlines and Sense Amplifiers in DRAM

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Isolation Transistor Between Bitlines and Sense Amplifiers in DRAM

Isolation transistors are used to decouple sense amplifiers (SAs) from various DRAM array sections, enabling array reuse and minimizing interference. In conventional designs, these transistors are typically turned off to isolate the reference bitline during single bitline load (SBL) operations. This isolation helps reduce power consumption by disconnecting the reference bitline from the precharge circuit in specific operations, such as in the proposed Single Bitline Write (SBW) and Single Bitline Load Sense Amplifier (SBLSA) circuits, which seek to minimize energy use during read and write stages. [1] In summary, the roles of isolation transistors are:

Isolation Transistor Function: The isolation transistor decouples bitlines from sense amplifiers, enabling parallel read and precharge operations. By disconnecting the sense amplifiers after activation, it allows precharging of bitlines while data remains accessible from the sense amplifiers, reducing latency.
Latency Management: Proper sizing of the isolation transistor minimizes activation latency. By using a high ON-resistance in the isolation transistor, it shields the sense amplifier from bitline load, which accelerates the sense amplification and lowers latency (tRCD), while having minimal impact on restoration latency (tRAS).
Power Efficiency: By tracking and adjusting row open times, the design controls idle power consumption in the sense amplifiers, especially under varying workloads.

Figure 1739a demonstrates the sense amplifier isolation with the added equalization isolation transistors, named as BLSAConnect, and shows how the isolation transistor decouples the bitlines from the sense amplifiers to enable simultaneous read and precharge operations.

Simultaneous read and precharge (SRP) mechanism: isolation of sense amplifiers and operational lverview

Figure 1739a. Simultaneous read and precharge (SRP) mechanism with the isolation transistors, named as BLSAConnect: isolation of sense amplifiers and operational lverview. [2]

[1] Dai, C.; Lu, Y.; Lu, W.; Lin, Z.; Wu, X.; Peng, C. "Low-Power Single Bitline Load Sense Amplifier for DRAM." Electronics, 12, 4024. https://doi.org/10.3390/electronics12194024, 2023.
[2] Subramanian, L.; Vaidyanathan, K.; Nori, A.; Subramoney, S.; Karnik, T.; Wang, H. Closed yet Open DRAM: Achieving Low Latency and High Performance in DRAM Memory Systems. In Proceedings of the ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 24–29 June 2018; pp. 1–6.

Integrated Circuits and Materials

An Online Book, First Edition by Dr. Yougui Liao (2018)

Isolation Transistor Between Bitlines and Sense Amplifiers in DRAM