Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix
| ATPG (Automatic Test Pattern Generation) is a key part of Design-for-Test (DFT) methodology. It refers to software tools and algorithms that automatically generate the test vectors (input patterns and expected outputs) used to detect manufacturing faults in digital circuits. Instead of engineers manually designing test cases, ATPG automatically creates patterns that can efficiently exercise the circuit to expose faults. ATPG relies heavily on scan chains, because they make flip-flops controllable and observable. Without scan, the tool might not be able to propagate faults to observable outputs.
Netlist + DFT (scan inserted)
│
├─► Choose fault models (SA, Transition, Bridging, …)
│
├─► ATPG search solves for activating + propagating patterns
│ (pattern compaction + X-filling as needed)
│
├─► Tester/DFT apply via scan:
│ 1) Shift-In (load scan FFs)
│ 2) Capture (functional clocks; at-speed for Transition)
│ 3) Shift-Out (unload responses)
│
└─► Compare to expected (or MISR signature in BIST/LBIST)
▷ Match → pass
▷ Mismatch → defect suspected → diagnosis
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