Electron microscopy
  
8F2, 6F2 and 4F2
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F is the feature size of the process technology. Feature size is either the minimum distance between the source and drain on a MOS transistor or half the distance between cells in a DRAM chip (known as "DRAM half pitch"). DRAM cell sizes are then measured using an nF2 formula where n is a constant. Bit sizes are measured in F2, which is the smallest feature you can create.

The cell architecture shown in Figure 2380a has been evolved from 8F2 cell to 6F2 cell since the cell size could be reduced up to 75% at the same design rule (F). [1]

3D cell architectures, showing that the cell size has been shrunk at the same design rule 3D cell architectures, showing that the cell size has been shrunk at the same design rule
(d) 4F2 cell showing vertical pillar transistor (VPT) [4]

Figure 2380a. 3D cell architectures, showing that the cell size has been shrunk at the same design rule (F) from 8F2 to 4F2 cell. [1] For 6F2, BL pitch=2F, WL pitch=3F.

Figure 2380b shows DRAM 8F2 cell structure:
        S/A -- Sense amplifier.
        WL -- Word-line.
        BL -- Bit-line.
        BLC -- Bit line contact.
        SNC -- Storage node contact.
        Cap -- Capacitor.

DRAM cell structure

Figure 2380b. DRAM 8F2 cell structure. [2]

DRAM cells have used an 8F2 architecture for many years. This design allows for the use of a folded bitline architecture, which helps reduce noise. [5] Comparing with 6F2, due to larger cell size, the 8F2 layout has two major advantages:
         i) The noise immunity is higher.
         ii) The process complexity is lower.

However, 6F2 cells can be used to decrease cell area with the same WL and BL pitchs. Figure 2380c shows the top view of a 6F2 cell, which is estimated as the simplest structure of the COB cells. This 6F2 cell has a 3F bitlines pitch and 2F wordlines pitch.

DRAM cell structure

Figure 2380c. DRAM 6F2 cell. [3]

Driving toward 4F2 cell size can further improve bit density and to lower production cost.

DRAM 4F2 VCAT cell structure

Figure 2380d. DRAM 4F2 VCAT cell structure. [2]

 

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[1] Yoosang Hwang, Jemin Park, Gyo-Young Jin, Chilhee Chung, An Overview and Future Challenges of High Density DRAM for 20nm and Beyond, the 2012 International Conference on Solid State Devices and Materials, Kyoto, 2012, pp586-587.
[2] https://blog.naver.com/minky0118/221860772321.
[3] Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura and Kiyoo Itoh, A Multigigabit DRAM Technology With 6F2 Open-Bitline Cell, Distributed Overdriven Sensing, and Stacked-Flash Fuse, DOI:10.1109/4.962294, IEEE International Solid-State Circuits Conference, 2001.
[4] Seong Keun Kim and Mihaela Popovici, Future of dynamic random-access memory as main memory, MRS Bulletin , 43(5), Materials for Advanced Semiconductor Memories, pp. 334 - 339, DOI: https://doi.org/10.1557/mrs.2018.95, (2018).
[5] http://chipworksrealchips.blogspot.com/2011/01/samsungs-3x-ddr3-sdram-4f2-or-6f2-you.html.

 
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