Integrated Circuits and Materials

Figure 2415a shows the potential distribution along the channel surface for long- and short-channel MOSFET devices. The potential barrier between the source and the channel prevents electron flow when the MOSFET is off. When the MOSFET is turned on (via V_GS), this barrier is reduced or eliminated, allowing electrons to move from the source to the drain. When a voltage is applied at the drain (V_DS), the drain potential reduces the height of the potential barrier near the drain region, effectively lowering the energy required for electrons to move from the source to the drain.

Because of the short channel effect (SCE) when DRAM shrinks down below 50 nm, various problems, such as the subthreshold current due to increased swing and drain induced barrier lowering (DIBL) and increased gate induced drain leakage (GIDL) due to higher doping, become more and more difficult to overcome. [1]

Table 2415. DIBL and other leakages.

Recess channel array transistor (RCAT) was introduced to solve SCE (short channel effect) in DRAM cell transistors. The recess gate structure of RCAT can reduce channel doping with increased channel length, and this increases the data retention time of the DRAM. However, the bottom curvature of the recess gate increases the subthreshold swing and the DIBL (drain induced barrier lowering), and its effect is amplified by the decreasing design rule [2]. The saddle-fin (S-fin) was then developed to suppress SCE and the bottom curvature effect by making a fin structure at the bottom channel of the RCAT, while keeping a good retention time character [3].

S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) technology is a modified structure of the RCAT (Recess-Channel-Array Transistor) and shows an excellent scalability of recessed-channel structure to sub-50 nm feature size. [4] Comparing to the RCAT structure, the S-RCAT demonstrated superior characteristics in:
          i) DIBL,
          ii) Subthreshold swing (SW),
          iii) Body effect,
          iv) Junction leakage current,
          v) Data retention time.

Figure 2415b shows that V_th and DIBL in S-RCAT increase due to decreasing radius of curvature(r_s) and effective channel length as the design rule gets scaled down. Increasing the recessed depth had been suggested to solve the deterioration of DIBL characteristic [5]. However, the curvature problem and uniformity become more severe by increasing the recessed depth.

Figure 2415b. As design rule shrinks in S-RCAT, V_th increases and DIBL deteriorates. [4]

[1] Min Soo Yoo, Kang Sik Choi, Woo Kyung Sun, Shin Gyu Choi, Jong Il Kim, Yun Ik Son, Hyoung-Gyu Choi, Tae Kyung Oh, Yun Taek Hwang, Yunseok Chun, Jae Goan Jeong, Sung Kye Park, Jae Hoon Choi, Sung Joo Hong and Sung Wook Park, Saddle-fin Cell Transistors with Oxide Etch Rate Control by Using Tilted Ion Implantation (TIS-Fin) for Sub-50-nm DRAMs, Journal of the Korean Physical Society, 56(2), pp.643∼647, 2010.
[2] J. Y. Kim, et al., Sym. on VLSI Technology Digest of Technical Papers, 33 (2005).
[3] S. W. Chung, et al., Sym. on VLSI Technology Digest of Technical Papers 32 (2006).
[4] J.Y. Kim, H.J. Oh, D.S. Woo, Y.S. Lee, D.H. Kim, S.E.Kim, G.W. Ha, H.J Kim, N.J. Kang, J.M. Park, Y.S. Hwang, D.I. Kim, B.J. Park, M. Huh, B.H. Lee, S.B. Kim, M.H. Cho, M.Y. Jung, Y.I. Kim, C. Jin, D.W. Shin, M.S. Shim, C.S. Lee*, W.S. Lee*, J.C. Park**, G.Y. Jin, Y.J. Park and Kinam Kim, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM feature size and beyond, Digest of Technical Papers. 2005 Symposium on VLSI Technology, DOI: 10.1109/.2005.1469201, 2005.
[5] J.Y. Kim et al., VLSI-TSA, Apr. 2005.
[6] H. Lee et al., “Fully integrated and functioned 44 nm DRAM technology for 1 GB DRAM,” in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2008, pp. 86–87, doi: 10.1109/VLSIT.2008.4588572.
[7] Zhang, S. (2020). Review of Modern Field Effect Transistor Technologies for Scaling. Journal of Physics: Conference Series, 1617, 012054. https://doi.org/10.1088/1742-6596/1617/1/012054.