Integrated Circuits and Materials

The Nsense and Psense amplifiers (NSA and PSA) in DRAM, as shown in Figure 4207a, are carefully designed to work together to:
          i) Correctly detect the access signal voltage.
          ii) Amplify the small signal voltage, produced during cell access (less than 200 mV), by driving the digitlines:
             ii.a) NSA with cross-coupled NMOS transistors drives the low-potential DL to ground through NLAT*.
             ii.b) PSA with cross-coupled PMOS transistors drives the high-potential DL to V_CC through ACT.

Critical consideration of the design of sense amplifiers are:
          i) Matching of transistor.
          ii) Transconductance.
          iii) Junction capacitance.
          iv) Overall balance of layout.
          v) All sources of noises, such as I/O lines and latch signals (NLAT* and ACT).
          vi) Lower subthreshold leakage and longer Refresh times by maintaining lower drain-to-source voltages (VDS) and negative gate-to-source voltages (VGS) across non-accessed mbit transistors.
          vii) Implement reduced latch voltages generally raise the NSA latch voltage without lowering the PSA latch voltage.

Figure 4207b shows sense amplifier schematic with I/O devices, indicating that:
          i) NSA pulls BL toward ground.
          ii) PSA pulls BL toward HIGH (namely, V_CC).

Initially, ACT is at V_SS (GND) and NLAT* held at V_CC/2. while both D1 (BL1) and D1* (BL1*) are at V_CC/2 as well. The start of the read operation is the node sense N, which have 0V voltage levels. When reading, the wordline is pulled to V_CC+V_th and BL1/* changes. After the cell has been accessed, a sense amplifier pulls up the voltage differential between the two column lines. The sensing is essentially the amplification of the differential voltage between the two column lines D1 and D1*. The P sense amplifier and the N sense amplifier are normally fired sequentially. The NSA is first fired by bringing NLAT* (N sense-amplifier latch) toward ground. The voltage difference between NLAT and the column lines increases so that the NMOS transistor whose gate is connected to the higher voltage column line begins to conduct. Such conduction causes the low-voltage column to be brought to discharge towards NLAT* and finally to be brought to ground voltage. However, the other NMOS transistor will not conduct. In some cases, after the N sense amplifier has fired, ACT (for active pull-up) will be brought towards VCC to activate the P snese amplifiers. The low-voltage column line is close to ground so that the corresponding PMOS transistor is driven into conduction. This charges the high-voltage column line towards ACT and ultimately towards V_CC. Therefore, all column lines are either driven to high or to low according to the contents of the DRAM cell in the row.

(a)

(b)

Figure 4207b. Sense amplifier schematic with I/O devices. The blocks marked by the green dots are copies of the circuits on the left. Sense P and sense N are complementary signals that are used with each SA to enable the sensing and amplification of the bitline voltage perturbation. Adapted from [1]

The Write driver simply overdrives the sense amplifiers. Figure 4207c shows the Write operation waveforms in DRAM.

[1] Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin, DRAM Circuit Design: Fundamental and High-Speed Topics , 2nd Edition, 2007.