Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix
| Conventional gate first integration involves the process of etching the gate material. For instance, Figure 4469a shows a nitride/W/TiN gate electrode stack on top of gate oxide. During the etching process, the gate electrode materials must be protected from oxidation or attack by wet chemicals. The gate electrode materials must also be stable with their surrounding materials during the heating steps at high temperatures. These requirements may limit the choices of materials for metal gate materials along with the alternative high-k dielectrics.
FinFET technology can be implemented using either the gate-first or gate-last approach, depending on the specific manufacturing process and design considerations. However, modern high-performance FinFET devices primarily adopt the gate-last process due to its advantages in device performance and reliability. In the gate-first process, the high-k metal gate stack is formed before the source and drain implantation and annealing steps. This method was initially used in early high-k metal gate (HKMG) implementations but posed challenges due to high-temperature processing, which could degrade the gate material and dielectric properties. Consequently, gate-first has become less common in advanced FinFET nodes.
[1] J. C. Hu, H. Yang, R. Kraft, A. L. P. Rotondaro, S. Hattangady, W. W. Lee, R. A.
Chapman, C. Chao, A. Chatterjee, M. Hanratty, M. Rodder, and I. Chen, "Feasibility
of using W/TiN as metal gate for conventional 0.13μm CMOS technology and
beyond," IEDM Tech. Dig., pp. 825 - 828, December 1997.
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