Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix
| Self-Aligned Double Patterning (SADP) is one of the important approaches for double patterning lithography (DPL) that addresses the limitations of traditional lithography methods, particularly at advanced technology nodes like 22 nm and beyond. For a fin pitch greater than 40nm, self-aligned double patterning (SADP) has been used with the resolution capability of 193nm wavelength immersion (193i) lithography. [1] SADP involves exposing a resist, developing it, and then depositing and etching a masking material to form sidewall spacers. The resist is then removed, and the substrate is etched using the spacers as a mask. The process concludes with removing the spacers to leave the final pattern as shown in Figure 4562. SADP is advantageous as it requires only a single critical exposure, minimizing overlay issues and providing improved critical dimension uniformities (CDUs) and line-edge roughness (LER). It meets the International Technology Roadmap for Semiconductors requirements for the 22 nm node, especially in memory applications. However, SADP is less suited to non-uniform designs, though recent advances propose adapting it for logic chips down to a 16 nm node with a 44 nm pitch.
[1] Ajey P. Jacob, Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee and Bill Taylor, Scaling Challenges for Advanced CMOS Devices, International Journal of High Speed Electronics and Systems, 26(01), 1740001, https://doi.org/10.1142/S0129156417400018, (2017).
|
