Integrated Circuits and Materials

Contacted Gate Pitch (CGP) is a fundamental parameter in semiconductor device scaling, particularly for Fin Field-Effect Transistor (FinFET) architectures used in modern CMOS (Complementary Metal-Oxide-Semiconductor) technologies. It is defined as the distance between the center of one gate to the center of the adjacent gate in a row of transistors, including the space occupied by the gate and the contact region. CGP effectively measures how closely gates can be placed to each other in an integrated circuit. CGP is important because it influences device density, scaling, and performance. As CGP decreases, more transistors can fit on a chip, improving performance and reducing costs per function. However, as CGP scales below 40 nm, challenges such as increased contact resistance arise, limiting the further scaling of traditional FinFETs. Figure 4704a shows the contacted gate pitch for a FinFET.

As FinFETs are scaled to smaller Contacted-Gate-Pitch (CGP) values (below 40 nm), the contact area between the transistor and its connections decreases. This reduction in contact area increases the contact resistance, which can significantly degrade the performance of the device. To counter this increase in resistance and maintain proper device functionality, the contact resistivity needs to be reduced. It was suggested that FinFETs scaled to a CGP below 40 nm will need a contact resistivity of approximately 8×10⁻¹⁰ Ω-cm² to maintain functionality. To further scale performance below a CGP of 30 nm, fully ohmic contacts with a resistivity of around 1×10⁻¹⁰ Ω-cm² will be required. [2] This value is necessary to keep the contact resistance within acceptable limits, preventing excessive power loss and ensuring the transistors can still drive sufficient current.

Figure 4704b shows the calculated contact resistance for thermionic, quantum tunneling, and fully ohmic contact resistivity values (ρC). The contact resistance exceeds the required limits for CGP values below 40 nm unless the contact resistivity is reduced to quantum tunneling levels (~8×10⁻¹⁰ Ω-cm²). Furthermore, it suggests that fully ohmic contacts, with resistivity as low as 1×10⁻¹⁰ Ω-cm², will be necessary to maintain FinFET performance at even smaller CGP values, such as below 30 nm​. 

[1] https://www.allaboutcircuits.com/news/ibm-and-samsung-teamup-to-defy-conventional-design/.
[2] Ali Razavieh, Peter Zeitzoff, E.J. Nowak, E.J. Nowak, Challenges and Limitations of CMOS Scaling for FinFET and beyond Architectures, IEEE Transactions on Nanotechnology, 18, DOI: 10.1109/TNANO.2019.2942456, 999, 2019.
[3] A. Razavieh, Y. Deng, P. Zeitzoff, M.H. Na, J. Frougier, G. Karve, D.E. Brown, T. Yamashita and E.J. Nowak, “Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters” DRC Proceedings, pp.
275-276 , June 2018.
[4] G. Timp, “Nanotechnology”.
[5] http://blog.appliedmaterials.com.