Integrated Circuits and Materials

Figure 4888a shows functional diagrams of DRAM. Here,
          C₁ - C₅ and R₁ - R₅ -- 10 address inputs. Each of them is connected to an on-chip address input buffer.
          Input buffers -- Drive the row (R) and co/umn (C) decoders, which have two purposes:
                 i) to provide a known input capacitance (C_IN) on the address input pins,
                 ii) to detect the input address signal at a known level so as to reduce timing errors.
          R/W* -- An input.
          CE* -- Can be low or high.

In DRAM, a sense amplifier is connected to a pair of bitlines.
        i) One bitline is the output data from a particular cell.
        ii) The other bitline is used as a reference line.

During sensing, the capacitor discharges or shares its stored charge with the bitline. This charge sharing then causes the voltage of the bitline either to increase or decrease.

Figure 4888c shows sense amplifier schematic with I/O devices. Initially, ACT is at V_SS (GND) and NLAT* held at V_CC/2. while both D1 (BL1) and D1* (BL1*) are at V_CC/2 as well. The start of the read operation is the node sense N, which have 0V voltage levels. When reading, the wordline is pulled to V_CC+V_th and BL1/* changes. After the cell has been accessed, a sense amplifier pulls up the voltage differential between the two column lines. The sensing is essentially the amplification of the differential voltage between the two column lines D1 and D1*. The P sense amplifier and the N sense amplifier are normally fired sequentially. The NSA is first fired by bringing NLAT* (N sense-amplifier latch) toward ground. The voltage difference between NLAT and the column lines increases so that the NMOS transistor whose gate is connected to the higher voltage column line begins to conduct. Such conduction causes the low-voltage column to be brought to discharge towards NLAT* and finally to be brought to ground voltage. However, the other NMOS transistor will not conduct. In some cases, after the N sense amplifier has fired, ACT (for active pull-up) will be brought towards VCC to activate the P snese amplifiers. The low-voltage column line is close to ground so that the corresponding PMOS transistor is driven into conduction. This charges the high-voltage column line towards ACT and ultimately towards V_CC. Therefore, all column lines are either driven to high or to low according to the contents of the DRAM cell in the row.

(a)

(b)

Figure 4888c. Sense amplifier schematic with I/O devices. The blocks marked by the green dots are copies of the circuits on the left. Sense P and sense N are complementary signals that are used with each SA to enable the sensing and amplification of the bitline voltage perturbation. Adapted from [1]

[1] Brent Keeth, R. Jacob Baker, Brian Johnson, and Feng Lin, DRAM Circuit Design: Fundamental and High-Speed Topics, (2007).