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Main CMOS Failure Mechanisms
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Table 1296a. Main CMOS Failure Mechanisms.

Technology generation Many failure mechanism [1]

0.50 µm

 Shallow trench isolation pull-down [1]
0.25 µm Aluminum interconnect failure and titanium silicide failure [1]
0.22 µm Cobalt silicide failure latchup [1]
0.18 µm MOSFET gate dielectric [1]
0.13 µm Power bus resistance [1]
90 nm Limited CDM failures [1]
65 nm Copper interconnects [1]
45 nm Tungsten contacts, and tungsten visa [1]
32 nm MOSFET source-drain strain [1]
22 nm FinFET source-to-drain, FinFET to FinFET failure [1]

Table 1296b lists main CMOS failure mechanisms in LOCOS (LOCal Oxidation of Silicon) technology.

Table 1296b. Main CMOS failure mechanisms in LOCOS technology.

LOCOS isolation Test polarity Pin pair (stress/reference) Failure mechanism Failure location [2]
N+ diffusion diodes Positive VSS Silicide penetration, metallurgical junction, contacts LOCOS bird's beak, metallurgical junction edge, contact-to-silicon surface [2]
P+ diffusion diodes Positive VDD Silicon melting, TiSi2 silicide resistance, contacts N-well under LOCOS, silicide surface [2]
N-well diodes Negative VSS Metallurgical junction failure   [2]
N-well to n-well Negative Well-to-well Molten silicon LOCOS isolation between wells [2]
N-channel MOSFET Positive Drain-to-source MOSFET second breakdown Molten silicon, MOSFET channel region [2]
Positive Gate Gate dielectric failure MOSFET gate [2]
P-channel MOSFET Negative Drain-to-source MOSFET second breakdown Molten silicon, MOSFET channel region [2]
Negative MOSFET gate Gate dielectric failure MOSFET gate [2]
N-well resistors

     Resistor second breakdown Resistor metallurgical junction, contacts [2]
N-well ballasted n-channel MOSFET Positive Drain-to-source MOSFET second breakdown Molten silicon [2]
Positive Gate Gate dielectric failure MOSFET gate [2]

Table 1296c. Shallow trench isolation (STI) failure mechanisms of CMOS.

STI Test polarity Pin pair (stress/reference) Failure mechanism Failure location [2]
N+ diffusion diodes Positive VSS Silicide penetration, metallurgical junction, contacts Junction surface, Metallurgical junction edge, contact-to-silicon surface [2]
P+ diffusion diedes Positive VDD Silicon melting, TiSi2 salicide resistance, CoSi2 agglomeration, contact N-well under shallow tranch isolation, silicide surface [2]
N-well diodes Negative VSS Metallurgical junction failure   [2]
N-well to n-well Negative Well-to-well Molten silicon Shallow trench isolation between wells [2]
N-channel MOSFET Positive Drain-to-source MOSFET second breakdown Molten silicon, MOSFET channel region [2]
Positive Gate Gate dielectric failure MOSFET gate [2]
P-channel MOSFET Negative Drain-to-source MOSFET second breakdown Molten silicon, MOSFET channel region [2]
Negative

MOSFET gate Gate dielectric failure MOSFET gate [2]
N-well resistors     Resistor second breakdown Resistor metallurgical junction, contacts [2]
N-well ballasted Positive Drain-to-source MOSFET second breakdown Molten silicon [2]
N-channel MOSFET Positive
 Gate Gate dielectric failure MOSFET channel region and gate [2]
Aluminum wire interconnect Positive   Aluminum melting Aluminum film [2]
Negative   Dielectric cracking Aluminum-ILD interface [2]
Tungsten first level Positive Signal pin ILD (inter-layer-dielectric) breakdown Tungsten film-to-polysilicon fill shape, ILD [2]
Tungsten stud contact     Tungsten melting Tungsten film, silicon surface [2]
Tungsten stud bar contact Positive   Tungsten melting Tungsten film [2]
Negative     Silicon surface [2]
Copper interconnect Positive   Copper melting Copper film [2]
Negative   Dielectric cracking Cracking at the Cu-ILD top surface [2]
Copper via Positive   Copper melting Copper film [2]
Negative     Cracking at the Cu-ILD top surface [2]
Copper dual damascene Positive   Copper film and via Displacement of Cu film and via [2]

Table 1296d. CMOS failure mechanisms in FinFET technology.

FinFETs Node Test polarity Failure mechanism [2]
MOSFET 65 nm Positive FinFET drain [2]
Drain-to-source Molten silicon [2]
45 nm Positive FinFET drain [2]
Drain-to-source Molten silicon [2]
32 nm Positive FinFET drain [2]
Drain-to-source Molten silicon [2]
Diode-configured FinFET 65 nm Positive FinFET fin region [2]
Drain-to-source [2]
45 nm Positive FinFET fin region [2]
Drain-to-source [2]
32 nm Positive FinFET fin region [2]
Drain-to-source [2]
FinFET   Positive p+/n+ fin region [2]
p-n gated diode   Anode-to-cathode Uniform conduction [2]

EOS (Electrical Overstress) failure mechanisms in CMOS technology can occur in all active and passive elements [1]:
         i) N-channel MOSFET,
         ii) P-channel MOSFET,
         iii) N-doped diffused resistors,
         iv) P-doped diffused resistors,
         v) Silicided polysilicon resistors,
         vi) Non-silicide polysilicon resistors,
         vii) Metal-oxide-metal capacitors,
         viii) Metal-insulator-metal capacitor,
         ix) Decoupling capacitors,
         x) Vertical natural plate (VNP) capacitors.

 

 

 

 

 

 

 

 

 

 

 

 

[1] Steven H. Voldman, Electrical Overstress (EOS): Devices, Circuits and Systems, 2013.
[2] Steven H. Voldman, ESD: Failure Mechanisms and Models, 2009.

 

 
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