Practical Electron Microscopy and Database

Table 2311. , band gap energies, and (CB) offsets Properties of the gate dielectrics on Si (silicon) substrate.

                                                                * CB: Conduction band.

The main problem with SiO₂ applied in scaling ICs is that electrons and holes can easily tunnel across the SiO₂ film if it is too thin (e.g. 1.4 nm for 45 nm node). Therefore, to avoid using too thin SiO₂ films in highly-scaled ICs, high-k dielectric materials should be employed. The selection of high-k dielectrics needs to satisfy several requirements:

       i) The dielectric constant (K) should be higher than 10, preferably 25−30. Too high K is also undesirable in CMOS design because of the strong fringing fields at source and drain electrodes [5].
       ii) The bandgap energy cannot be too small.

Combining i) and ii), there is a trade off between the two because the K varies inversely with the bandgap energy. Therefore, we normally accept a relatively low K value [6].

       iii) Highly chemical and electrical stability. The oxides are in direct contact with the Si channel, so they must be thermodynamically stable
with it.
       iv) Must act as insulators and have conduction band offsets, with Si, higher than 1 eV to minimize electron or hole injection into its bands.
       v) Must form a good electrical interface with Si.
       vi) Have not too high densities of electrically active defects. Instabilities can be caused by the high defect densities.
       vii) Do not lose carrier mobility in the Si channel when using high K oxides.
       viii) Have proper metal gates to satisfy the needs of high k dielectrics.

Further requirement is:

       ix) The ability to continue scaling to lower dielectric thickness.

In EELS, perovskite type ferroelectric and high-k dielectric materials, such as BaTiO₃ and SrTiO₃, normally show only one interband plasmon peak [1–4].

[1] K.S. Katti, M. Qian, F. Dogan, M. Sarikaya, J. Am. Ceram. Soc. 85 (2002) 2236–2243.
[2] K. van Benthem, C. Elsasser, R.H. French, J. Appl. Phys. 90 (2001) 6156–6164.
[3] S. Schamm, G. Zanchi, Ultramicroscopy 88 (2001) 211–217.
[4] J. Zhang, A. Visinoiu, F. Heyroth, F. Syrowatka, M. Alexe, D. Hesse, H.S. Leipner, Phys. Rev. B 71 (2005) 064108.
[5] R. Chau, at International Workshop on Gate Insulator, Tokyo, (2003).
[6] J. Robertson, J. Vac. Sci. Technol. B 18, 1785 (2000).