This book (Practical Electron Microscopy and Database) is a reference for TEM and SEM students, operators, engineers, technicians, managers, and researchers.
 

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Due to the continuous scaling of CMOS, the thickness of the SiO₂ layer used as the gate dielectric is so thin (under 1.4 nm) that the gate leakage current due to the direct tunnelling of electrons through the SiO₂ layer becomes too high (exceeding the maximum tolerable gate leakage current 1 Acm⁻² at 1V) as shown in Figure 2913, therefore, the power dissipation dramatically increases to unacceptable values [1–6]. Note that the leakage current limit in DRAM is also indicated in the figure. On the other hand, the reliability of the SiO₂ films against electrical breakdown declines in the thin films.

[1] Wilk G, Wallace R M, Anthony J M, 2001 J. Appl. Phys. 89 5243
[2] Wallace R M and Wilk G D 2003 Crit. Rev. Solid State Mater. Sci. 28 231
[3] Robertson J 2004 Eur. Phys. J. Appl. Phys. 28 265
[4] Huff H and Gilmer D (ed) 2004 High K gate Dielectrics (Berlin: Springer)
[5] Houssa M (ed) 2003 High Dielectric Constant Materials: VLSI MOSFET Applications (London: IOP)
[6] Demkov A A and Navrotsky A (ed) 2005 Materials Fundamentals of Gate Oxides (Dordrecht: Springer)
[7] Lo S. H., Buchanan D. A., Taur Y. and Wang W., Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET’s, (1997) IEEE Electron Device Lett. 18 209.