Wafer bin Map

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Wafer Bin Map

A wafer bin map (WBM), which is the result of an electrical die-sorting test, provides information on which bins failed and plays an important role in finding defective wafer patterns in semiconductor integrated circuits (IC) manufacturing. Wafer inspection based on WBM currently has two main problems:

Good/bad WBM classification is performed by engineers.
Bin code coloring scheme does not reflect the relationship between bin codes.

A WBM is a database system that collects and visualizes data regarding physical parameters that are measured on IC wafers. Such maps contain measurement data and various metrology tools, such as ellipsometers, thickness gauges, and four point probes as well as information such as the location and size of defects. The wafer map analysis extracts and processes information about defects, such as particles, extra materials, and holes on wafers [1]. There are mainly two types of wafer inspection:

Human inspection of defects in wafer map. (see page4261).
Automated defect scanning in wafer map. (see page4260).

Figure 0159 presents a Wafer Bin Map, which shows different yield loss events across the wafer, with each sub-image representing specific systematic or random yield loss patterns, such as edge or center yield losses. Each yield loss event is mapped to illustrate its spatial distribution across the wafer, characteristic of a Wafer Bin Map's function in visualizing die-level binning across the entire wafer.

Wafer Bin Map illustrating various yield loss events, including systematic edge and center losses, localized and repeated yield losses, and random yield loss patterns. Each sub-map visualizes the spatial distribution of these failures across the wafer, aiding in identifying defect trends associated with different yield loss mechanisms

Figure 0159. Wafer Bin Map illustrating various yield loss events, including systematic edge and center losses, localized and repeated yield losses, and random yield loss patterns. Each sub-map visualizes the spatial distribution of these failures across the wafer, aiding in identifying defect trends associated with different yield loss mechanisms. [1]

[1] Hsieh, Y.-L., Tzeng, G.-H., Lin, T. R., & Yu, H.-C., Wafer Sort Bitmap Data Analysis Using the PCA-Based Approach for Yield Analysis and Optimization. IEEE Transactions on Semiconductor Manufacturing, 23(4), 493–503. https://doi.org/10.1109/TSM.2010.2065510, 2010.

Integrated Circuits and Materials

An Online Book, First Edition by Dr. Yougui Liao (2018)

Wafer Bin Map