Read from SRAM

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Read from SRAM

Figure 0173a illustrates the layout and equivalent circuit of a 6T SRAM cell embedded in a 0.25-μm generation microprocessor. [1] The left side of the figure shows the physical layout of the SRAM cell, and the right side shows the equivalent circuit schematic. This SRAM cell design is used in an application for high-frequency and low-voltage modes.

6T (6-Transistor) SRAM

Figure 0173a. 6T SRAM cell layout embedded on a 0.25-μm generation microprocessor (left) and its equivalent circuit (right). Adapted from [1]

The output of a read operation in SRAM is typically routed from either the bitline (BL) or bitline-bar (BL-bar), depending on the state of the cell's data. When reading, the selected cell are mirrored on both the bitline and bitline-bar, where one will represent the data (logic high or low) and the other its complement. The sense amplifier connected to these lines interprets the differential signal and amplifies it to drive the output pin, ensuring accurate data retrieval.

The 6T SRAM cell stores a single bit of data by holding it in a stable state within a cross-coupled inverter pair. Table 0173 shows the truth table for such a 6T SRAM cell.

Table 0173. Truth table for such a 6T SRAM cell presented in Figure 0173a.

Operation	Tr-NMOS Gates		Drain of Tr-NMOS		Drain of Tr-NMOS		Node Q	Node QB
Operation	Tr-NMOS	WL (Word Line)	Tr-NMOS	BL (Bit Line)	Tr-NMOS	BLB (Bit Line Bar)	Node Q	Node QB
Hold	Off	Low		—		—	Stable (either 0 or 1)	Stable (either 0 or 1)
Read '1'		High		High		Low	High	Low
Read '0'		High		Low		High	Low	High
Write '1'		High		High		Low	High	Low
Write '0'		High		Low		High	Low	High

In the 6T SRAM cell shown in Figure 0173a, during a read operation to detect a stored '1,' the cell operating conditions, as shown in Figure 0173b, are as follows:

Assume:
- Word Line (WL) is low (=0).
- Q is low (=0), thus QB is high (=1).

Activated Transistors:
- The two access transistors (Tr-NMOS) are activated by the Word Line (WL), which connects the storage nodes to the bit lines (Data Lines) for reading.
- The load PMOS transistor (Ld-PMOS) connected to the node storing "1" will be on (active) to pull the node to Vcc, thus representing a stable high state.

Non-Activated Transistors:
- The driver NMOS transistor (Dr-NMOS) on the same side as the "1" state is off (inactive), as it does not need to pull the node to ground.
- On the opposite side (storing "0"), the Ld-PMOS is off, and the Dr-NMOS is on to pull that node to ground, maintaining the "0" state.

Precharged Lines:
- Both bit lines (Data Lines) are precharged to a high voltage level (usually Vcc) before the word line is activated. This precharge allows the sense amplifier to detect a differential voltage change when the access transistors connect the storage nodes to the bit lines. The precharging process does not directly activate the transistors inside the SRAM cell (like the Tr-NMOS, Ld-PMOS, and Dr-NMOS transistors). Instead, it is typically managed by a precharge circuit outside the SRAM cell that pulls the bit lines to Vcc.

During reading:
- BLB is precharged to VCC/2, while BL is discharged to ground as shown in Figure 0173c. During a read operation, the bit-lines are initially precharged to a common intermediate voltage before accessing any cell. This precharge process, however, can be relatively slow due to the limited drive strength of the minimized transistors within each cell, which are designed for high density rather than speed. Once the cell is accessed, a small differential voltage develops between BL and BLBar, reflecting the stored data. At this stage, the sense amplifier plays a critical role, not by accelerating the precharge itself, but by rapidly detecting and amplifying this small differential signal to drive it to a full logic level.