Integrated Circuits and Materials

An Online Book, First Edition by Dr. Yougui Liao (2018)

Practical Electron Microscopy and Database - An Online Book

Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix

Litho-Etch-Litho-Etch (LELE)/Pitch Splitting

Litho-etch-litho-etch (LELE) is a form of double patterning. LELE is also called pitch splitting. Figure 2390a illustrates the LELE double patterning process. LELE is a straightforward double patterning method involving two cycles of lithography and etching to create a final pattern. The first lithography step is followed by an etching step, and this sequence is repeated for the second layer. This technique requires two masks, doubling both the time and cost of fabrication due to the added steps. However, it faces challenges such as strict overlay tolerance, where even a slight misalignment of the second pattern can result in defects in the final design​.

LELE double patterning process
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Figure 2390a. LELE double patterning process: (a) The initial pattern (in yellow) is transferred onto a hard mask through exposure, (b) The initial pattern is transferred into the hard mask layer (depicted in brown), (c) A second pattern (yellow) is applied onto the silicon layer (blue), effectively increasing the pattern density, (d) The silicon is etched to achieve the final double-density pattern., and (e) The residual mask is removed. [1] Note that in standard lithography, the layer in yellow is normally a photoresist material, while the layer in brown could represent an underlying material layer, such as silicon or a silicon oxide layer, that will be etched after the patterning. However, since the layer in blue is silicon, the layer in brown should be a silicon oxide layer.

Figure 2390b shows the LELE process plays a crucial role in achieving fine feature resolution at advanced nodes such as 22 nm. LELE involves two sequential lithography and etching steps to define a densely packed pattern on the substrate. First, a photoresist layer is applied and patterned via lithography, followed by an etching step to transfer this initial pattern onto the substrate. Next, a second layer of photoresist is applied, aligned precisely with the first pattern, and exposed to define additional features in a complementary manner. A subsequent etch step completes the process, creating the final, high-resolution pattern. While LELE enables tighter feature control, it introduces significant challenges in overlay alignment and process complexity, particularly as feature sizes approach the 22 nm scale, where even minor misalignments can impact device performance and yield. In such double patterning lithography, hard masks typically consist of durable materials such as silicon nitride (Si3N4), silicon dioxide (SiO2), or titanium nitride (TiN), as they provide the necessary etch resistance and thermal stability for complex patterning processes.

LELE approach
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Figure 2390b. LELE approach: (a) Lithography (first exposure), (b) First etching, (c) Second lithography (second exposure), and (d) Second etching. [4]

LELE is integral in advanced nodes (e.g., 14 nm and below) due to the need for precise overlay (layer alignment), which is essential for device functionality. In LELE technology, the step most prone to inducing defects is the second lithography step. This stage is especially challenging due to the precise overlay tolerance required to align the second pattern accurately with the first. Even a slight misalignment between the two patterns can cause overlay defects—resulting in pattern distortions, unintended feature shifts, or critical dimension (CD) variations that directly impact the device performance and yield. The need for precise alignment in this second lithography step increases the risk of defects due to:

  • Misalignment between the two patterns, causing non-uniformities. Misalignments in LELE can cause significant issues, such as shorts or device failure, impacting yield and reliability.
  • Critical dimension mismatches where the second pattern doesn’t perfectly overlay the first.
  • Edge placement errors due to the small scale of features at advanced nodes, where even minor errors can lead to significant defects.
  • LELE and subsequent multi-patterning techniques, like LELELE and self-aligned processes, increase the number of critical masks required. This complexity demands tighter overlay controls, as even small deviations can drastically affect device performance.
  • Traditional image- and diffraction-based overlay measurement methods face limitations in precision and are challenged by issues like low contrast and tool-induced shifts (TIS). These methods struggle with the stringent overlay specifications necessary in LELE-based processes.

Figure 2390c illustrates the experimental setup for evaluating overlay control through an electrical misalignment (eMA) measurement technique. This setup comprises a macro structure with two metal nest layers connected by via chains, designed to assess the alignment precision between layers patterned in successive litho-etch steps. To simulate overlay errors, the top layer from the second litho-etch cycle is intentionally shifted relative to the bottom layer, with displacements applied in both positive and negative directions along the X and Y axes. By plotting the electrical resistance as a function of these controlled misalignments, the study demonstrates a parabolic relationship where the minimum point indicates optimal overlay. This method allows for precise quantification of overlay control, providing critical insights into alignment tolerances required to enhance yield and reliability in multi-patterning lithography processes. That is, this misalignment setup simulates potential overlay errors between layers deposited and patterned in successive litho-etch cycles, allowing researchers to assess the impact of misalignments on electrical resistance and overlay control.

(a) Macro design featuring metal nest structures connected by vias, (b) configuration without via-to-metal misalignment, (c) configuration showing intentional misalignment between via and underlying metal, and (d) transmission electron micrographs illustrating the reduction in contact area as misalignment increases.

Figure 2390c. (a) Macro design featuring metal nest structures connected by vias, (b) configuration without via-to-metal misalignment, (c) configuration showing intentional misalignment between via and underlying metal, and (d) transmission electron micrographs illustrating the reduction in contact area as misalignment increases. [3]

 

 

 

 

 

 

 

 

 

[1] Amirtharaj, M., & Kruder, Z. (Year). Double Patterning and Hyper-Numerical Aperture Immersion Lithography. ENEE416. 
[2] Zhou, W., Wei, F., Zhang, Y., Zhu, J., Hu, C.-Y., Cho, K., Corradi, A., Pao, K.-F., Jain, V., Elmalk, A., Raghunathan, S., Hunsche, S., Zhu, R., Chen, S., Lin, L., Liang, L., & Liu, L. (2021). Contour-based metrology for assessment of edge placement error and its decomposition into global/local CD uniformity and LELE intralayer overlay. In Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV (Vol. 11611, 116111Y). SPIE. https://doi.org/10.1117/12.2584654.
[3] Devender, Shen, X., Duggan, M., Singh, S., Rullan, J., Choo, J., ... & Sohn, D. K. (2017). High throughput electrical characterization for robust overlay lithography control. Proceedings of SPIE, 10145, 101450K. https://doi.org/10.1117/12.2260707.
[4] Zimmerman, P. (2009). "Double Patterning Lithography: Double the Trouble or Double the Fun." SPIE Newsroom.