Chapter/Index: Introduction | A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | Appendix
| EPE (Edge Placement Error) is a metric that measures how far the actual edges of a feature on a semiconductor device deviate from their intended position. Minimizing EPE is critical for ensuring that the device functions correctly. This measurement is increasingly important as device dimensions shrink, resulting in tighter process margins and a heightened need for accurate characterization of EPE to ensure in-line process control. For instance, researchers highlights the decomposition of EPE into components such as global and local critical dimension uniformity (CDU) and intra-layer overlay within a litho-etch-litho-etch (LELE) process. [1] This decomposition reveals that intra-layer overlay errors significantly contribute to the overall EPE budget, underscoring the need to monitor layer-to-layer alignment accuracy. In this case, they utilize contour-based SEM metrology to assess and break down EPE by capturing not only feature sizes but also local placement variations and shapes. This approach allows for precise mapping of both local and global errors, identifying specific regions on the wafer that exhibit the highest variability. A detailed EPE budget breakdown in the study shows that local placement errors are the dominant contributors, with the first and second litho-etch layers contributing over 35% and 40% of the total EPE budget, respectively. In addition, the study examines wafer-to-wafer variation, noting that differences in global and local CDU and overlay components between wafers further emphasize the importance of continuous EPE monitoring. The decomposition of EPE into its constituent sources provides valuable insights for process control, enabling targeted improvements in precision and yield. This methodology not only assists in pinpointing specific contributors to EPE but also enhances defect monitoring, thereby reducing defect rates and improving the overall efficiency of semiconductor manufacturing. Through this analysis, EPE emerges as a comprehensive error metric, combining global overlay, CDU errors, and local placement errors, offering a complete budget for evaluating pattern fidelity and maintaining robust process performance. The primary components of EPE for LELE process are:
Wafer-to-Wafer Variation: The wafer-to-wafer EPE differences involve normalized EPE values and the percentage contributions of each EPE component for comparison across wafers. This analysis would likely involve calculating normalized EPE max values for each wafer and comparing the percentage breakdowns of CDU and overlay contributions.
[1] Zhou, W., Wei, F., Zhang, Y., Zhu, J., Hu, C.-Y., Cho, K., Corradi, A., Pao, K.-F., Jain, V., Elmalk, A., Raghunathan, S., Hunsche, S., Zhu, R., Chen, S., Lin, L., Liang, L., & Liu, L. (2021). Contour-based metrology for assessment of edge placement error and its decomposition into global/local CD uniformity and LELE intralayer overlay. In Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV (Vol. 11611, 116111Y). SPIE. https://doi.org/10.1117/12.2584654.
|