Integrated Circuits and Materials

A scan chain is a sequence of flip-flops connected together in a way that allows test data to be shifted in and out during the testing of integrated circuits. The purpose is to make internal states of the circuit observable and controllable, which would otherwise be hidden deep inside the design. By shifting in test patterns, engineers can stimulate specific parts of the circuit, and by shifting out the captured responses, they can check whether the circuit behaves as expected. If the observed data differs from the expected results, it points to a fault in the logic or interconnections. This mechanism is fundamental to Design-for-Test (DFT) methodology because it provides a structured and efficient way to diagnose faults without requiring physical access to each internal node of the chip.

The flip-flops are the same kind of basic storage elements repeated many times. Each flip-flop is a small digital circuit (usually D-type) that stores one bit of data. In a scan chain, every flip-flop is augmented with a small multiplexer (MUX), shown in Figure 0240b, so it can operate in two modes:

• Normal mode: it works as a standard register in the circuit, capturing data from the functional logic. This is the chip’s standard operating mode, where flip-flops capture functional data from the circuit and the device performs its intended logic.

• Scan mode: it connects to its neighbor flip-flops in the chain, so test data can be shifted through all of them like a long shift register. This is mainly used for manufacturing test, fault detection, and debugging, not just troubleshooting in the lab. In production, scan chains are used to systematically apply test patterns (generated by ATPG – Automatic Test Pattern Generation tools) to detect defects such as stuck-at faults, bridging faults, or timing issues.

Therefore, while each flip-flop is structurally the same unit, its position in the chain and the surrounding logic determine what piece of functional data it stores during normal operation. Each rectangle (FF1, FF2, FF3, FF4) is a flip-flop in Figure 0240a.

Figure 0240a. Flip-flops linked in scan mode (shift register).

Figure 0240b. Scan enable signal controls each MUX (choose Normal or Scan path).

Note that a MUX is a digital circuit that selects one of several input signals and forwards it to a single output, based on control signals (called select lines). For instance, a 2-to-1 MUX has two data inputs, one select input, and one output. If the select input = 0, the output follows input 0; if select = 1, the output follows input 1. Each MUX selects between Normal Data (from the circuit’s logic) and the Scan In path. The selection is controlled by a Scan Enable signal:

• When Scan Enable = 0, the flip-flop captures the normal functional data.

• When Scan Enable = 1, the flip-flop becomes part of the scan chain and shifts in test data.

The outputs propagate from one flip-flop to the next, with the last one providing Scan Out. The MUX chooses between the normal data input and the scan data input. The select line is the Scan Enable signal, which controls whether the flip-flop works in normal mode or scan mode.