Electron microscopy
  
     
Feature Size/Smallest Critical Dimension and Lithography History
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F is the feature size of the process technology. The critical dimension (CD) of a layer is proportional to the feature size. The feature size control parameters are depth of focus (DOF) and exposure latitude (EL), while the feature placement parameters are alignment accuracy, magnification, and rotations. Feature size is either the minimum distance between the source and drain on a MOS transistor or half the distance between cells in a DRAM chip (known as "DRAM half pitch"). DRAM cell sizes are then measured using an nF2 formula where n is a constant. Bit sizes are measured in F2, which is the smallest feature you can create.

Table 2366. Practical (smallest) feature size with different lithography technologies and lithography history.

Feature size Technology Applications Company Time Product Referece
43 nm pillars at 86 nm pitch Single exposure ArF immersion     Feb 2021   [7]
39 nm pillars at 78 nm pitch

Double exposure ArF immersion litho where two perpendicular line/space (L/S) structures are exposed with single resist coating

     Feb 2021   [7, page2389]
38 nm Limit of single patterning using ArF immersion lithography (Figure 2366a)         [6]
  Multipatterning + 193-nanometer immersion 15% more power efficient and 35% more dense then the previous version
   Nov 2022 DRAM [2]
28 nm EUV ADT   IMEC     [6]
22 nm EUV scanners resolution       DRAM page4849
21 nm pillars at 42 nm pitch Single exposure EUV     Feb 2021   [7]
20 nm Limit of DPT or SPT using ArF immersion lithography (Figure 2366a)         [6]
20 nm EUV       DRAM [1]
19 nm Limit of pitch doubling by ArF immersion         page2287
16/14 nm EUV       DRAM page4849
16/14 nm 193 nm immersion + double patterning       DRAM page4849
14 nm EUV Applied EUV DDR5 DRAM and has boosted productivity by 20% Samsung Oct 2021 DRAM [4]
10 nm EUV LPDDR4 mobile DRAM, EUV enables it to gain 25% more chips on the same size wafer, translating into 25% density improvement SK Hynix Jul 2021 DRAM [3]
Below 10 nm   1-alpha/1-beta node node Micron May 2022 DRAM [5]
7 nm Single patterning is possible with EUV, but slow operation       DRAM page4849
5 nm EUV + double patterning          
 
More history
 

EUV and high-index fluid-based immersion ArF lithography are questionable whether they will be ready to timely meet resolution needs of most aggressive memory designs.

     2007   [8]

Resolution limit of ArF immersion lithography

Figure 2366a. Resolution limit of ArF immersion lithography. [6]

Total delay vs. minimum feature size

Figure 2366b. Total delay vs. minimum feature size. [9]

 

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[1] Kanghyun Kim, Jong-Won Lee, Byeong-Gyu Park, Hyun-Taek Oh, Yejin Ku, Jin-Kyun Lee, Geunbae Lim and Sangsul Lee, Investigation of correlative parameters to evaluate EUV lithographic performance of PMMA, RSC Advances, 2022, 12, 2589.
[2] https://spectrum.ieee.org/micron-dram.
[3] https://www.tomshardware.com/news/sk-hynix-1anm-dram-euv.
[4] https://www.zdnet.com/article/samsung-applies-euv-to-ddr5-dram/.
[5] https://www.techpowerup.com/295419/micron-moving-to-euv-lithography-in-taiwan.
[6] Tae-Seung Eom, Sarohan Park, Jun-Taek Park, Chang-Moon Lim, Sunyoung Koo, Yoon-Suk Hyun, HyeongSoo Kim, Byung-Ho Nam, Chang-Reol Kim, Seung-Chan Moon, Noh-Jung Kwak, Sungki Park, Comparative study of DRAM cell patterning between ArF immersion and EUV lithography, https://doi.org/10.1117/12.814378, SPIE Advanced Lithography, 2009.
[7] Murat Pak, Wesley Zanders, Patrick Wong, Sandip Halder, Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars, Micro and Nano Engineering, https://doi.org/10.1016/j.mne.2021.100082, 2021.
[8] Mircea Dusa, John Quaedackers, Olaf F. A. Larsen, Jeroen Meessen, Eddy van der Heijden, Gerald Dicker, Onno Wismans, Paul de Haas, Koen van Ingen Schenau, Jo Finders, Bert Vleemingb, Geert Storms, Patrick Jaenen, Shaunee Cheng, Mireille Maenhoudt, Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets, Proceedings of SPIE - The International Society for Optical Engineering 6520, DOI: 10.1117/12.714278, 2007.
[9] S.P. Murarka, Metallization: Theory and Practice for VLSI and ULSI, Butterworth-Heinemann, Boston, 1993.




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