| Resolution enhancement technologies (RET), such as hyper-NA immersion
lithography, polarized illumination, double patterning technology (DPT) and spacer patterning technology (SPT), have extended the limitation of optical lithography. During DRAM scaling, the number of ArF-i DPT layers has been increasing sharply due to immature EUV lithography with a wavelength of 13.5 nm. [1] However, DPT and SPT are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. [3]
Figure 2389a shows the lithography technologies have been developed. Not
only scaling down the wavelength but also using DPT process
will be more and more important. [2]
Figure 2389a. Lithography technologies. [2] |
For double exposure ArF immersion lithography, two perpendicular line/space (L/S) structures, as shown in Figure 2389b, are exposed with single resist coating to achieve
39 nm pillars at 78 nm pitch.
Figure 2389b. Perpendicular L/S masks used for pillar printing with double expo
sure approach. [4] |
| Table 2389. Comparison between different double patterning lithography (DPL) techniques. [5] |
| DP Approach |
Advantages |
Disadvantages |
| Litho-etch, litho-etch (LELE) |
No fundamental limitations ≥ 22nm |
Costly extra processing
Challenging overlay for ≤ 22nm |
| Litho-Freeze Litho-Etch (LFLE) |
No fundamental limitations ≥ 22nm
Intermediate processing possible on track |
Costly extra processing
Challenging overlay for ≤ 22nm |
| Self-aligned double patterning (SADP) |
Single critical exposure, other processing steps are done offline on less expensive tools.
More cost-effective than LELE or Litho-freeze.
No overlay issues → Better scalability.
Currently applicable to memory patterning.
Best line-edge/linewidth roughness and critical dimension uniformities. |
Need to modify design for 2D applications.
Significant extra processing required. |
| Dual-tone development (DTD) |
Improved cost-effectiveness |
New materials development required.
Negative-tone materials historically difficult.
Does not currently meet 32nm requirements.
Challenging overlay for ≤ 22nm.
Line-edge/linewidth roughness may be a show stopper. |
| Double exposure (DE) |
Best overall cost
No overlay issues |
Materials not currently available.
Material integration may be difficult.
No intrinsic improvement for.
Line-edge/linewidth roughness, which may limit applicability below 22nm |
[1] J. M. Park; Y. S. Hwang; S.-W. Kim; S. Y. Han; J. S. Park; J. Kim; J. W. Seo; B. S. Kim; S. H. Shin; C. H. Cho; S. W. Nam; H. S. Hong, 20 nm DRAM: A new beginning of another revolution, 2015 IEEE International Electron Devices Meeting (IEDM), DOI: 10.1109/IEDM.2015.7409774, 2015.
[2] Yoosang Hwang, Jemin Park, Gyo-Young Jin, Chilhee Chung, An Overview and Future Challenges of High Density DRAM for 20nm and Beyond, the 2012 International Conference on Solid State Devices and Materials, Kyoto, 2012, pp586-587.
[3] Tae-Seung Eom, Sarohan Park, Jun-Taek Park, Chang-Moon Lim, Sunyoung Koo, Yoon-Suk Hyun, HyeongSoo Kim, Byung-Ho Nam, Chang-Reol Kim, Seung-Chan Moon, Noh-Jung Kwak, Sungki Park, Comparative study of DRAM cell patterning between ArF immersion and EUV lithography, https://doi.org/10.1117/12.814378, SPIE Advanced Lithography, 2009.
[4] Murat Pak, Wesley Zanders, Patrick Wong, Sandip Halder, Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars, Micro and Nano Engineering, https://doi.org/10.1016/j.mne.2021.100082, 2021.
[5] Zimmerman, P. (2009). "Double Patterning Lithography: Double the Trouble or Double the Fun." SPIE Newsroom.
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